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DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 1 of 74 ? 2015 dialog semiconductor gmbh 1. g eneral d escription DA9211 and da92 12 are pmu s optim ise d for the supply of cpus, gpus, and ddr memory rails in smartphones, tablets and other handheld applications. t he fast transient response (10a/s) and load regulation are optim ise d for the new generation of multi - core application processors . da9212 integrates two dual - phase buck converters, each phase using a small external 0.47 h inductor. each buck is capable of delivering up to 6 a output current at an output voltage in the range 0.3 - 1.57 v. the input voltage range of 2. 8 C 5.5 v makes it suited for a wide variety of low voltage systems, including all li - ion battery - powered applications. DA9211 operate s as a single four - phase buck converter delivering up to 12 a out put current . to guarantee the highest accuracy and to support multiple pcb routing scenarios without loss of performance, a remote sensing capability is implemented in both DA9211 and da9212 . the power devices are fully integrated, so no external fets or s c hottky diodes are needed. a programmable soft start - up can be enabled, which limits the inrush current from the input node and secures a slope - controlled activation of the rail. the dynamic voltage control (dvc) supports adaptive adjustment of the supply voltage depend ing on the processor load , either via direct register write s through the communication interface (i2c or spi compatible) or via a n input pin. a voltage track ing functio nality is implemented allowing the buck output voltage to be controlled by an analog ue input signal. t his feature, t ogether with a digital clock input, allow s complete control of the buck converter from external signals in the platform. DA9211 and da9212 feature integrated over - temperature and over - current protection for increased system reliability without the need for external sensing components. the safety feature set is completed by a v ddio under voltage lockout. the configur able i2c address selection via gpi allows multiple instances of DA9211 and da9212 or both to be placed in the application sharing the same communication interface with different addresses. 2. key f eatures 2. 8 v to 5.5 v input voltage 0.3 v to 1.57 v output voltage 12 a output current (DA9211) 2x 6 a output current (da9212) 3 mhz nominal switching frequency max inductor height 1.0 mm 1 % accuracy (static) 3 % accuracy ( dynamic) dynamic voltage control (dvc) automatic phase shedding integrated power switches remote sensing at point of load i2c/spi compatible interface output voltage t racking capability adjustable soft start - 40 to +85 oc temperature range package 42 wl - csp 0.4 mm pitch
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 2 of 74 ? 2015 dialog semiconductor gmbh 3. a pplications smartphones, mobile phones and ultra books tablet pcs, e - book readers and car infotainment portable navigation devices, tv and media players 4. system d iagram s figure 1 : DA9211 system diagram v s y s f b a p r e g i s t e r s p a c e o t p m e m o r y d i g i t a l c o r e 2 / 4 - w i r e i n t e r f a c e v d d i o b i a s s u p e r v o s c g p i 1 o u t n i r q 4 x 0 . 4 7 h 4 x 1 0 f s c l / s k i n l / c / r p c b g p i 0 1 f v d d _ a 1 v d d _ a 2 v d d _ b 1 v d d _ b 2 g p i g p i 1 0 0 n f g p i o 2 g p i o v s s _ a n a s d a / s i g p i o p o l f b a n f b b p f b b n 4 x 2 2 f i c _ e n i n s o / g p i o 3 n c s / g p i 4 g p i o d v s c t r l + d r i v e
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 3 of 74 ? 2015 dialog semiconductor gmbh figure 2 : da9212 system diagram v s y s f b a p d v s d a c r e g i s t e r s p a c e o t p m e m o r y d i g i t a l c o r e 2 / 4 - w i r e i n t e r f a c e v d d i o c t r l + d r i v e b i a s s u p e r v o s c g p i 1 o u t n i r q 2 x 0 . 4 7 h 4 x 1 0 f s c l / s k i n l / c / r p c b g p i 0 1 f v d d _ a 1 v d d _ a 2 v d d _ b 1 v d d _ b 2 g p i g p i 1 0 0 n f d v s d a c c t r l + d r i v e g p i o 2 g p i o v s s _ a n a s d a / s i g p i o p o l f b a n f b b p f b b n 2 x 2 2 f i c _ e n i n s o / g p i o 3 n c s / g p i 4 l / c / r p c b p o l 2 x 2 2 f b u c k a b u c k b g p i o 2 x 0 . 4 7 h
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 4 of 74 ? 2015 dialog semiconductor gmbh contents 1. general description ................................ ................................ ................................ ....................... 1 2. key features ................................ ................................ ................................ ................................ ... 1 3. application s ................................ ................................ ................................ ................................ ... 2 4. system diagrams ................................ ................................ ................................ ........................... 2 5. revision history ................................ ................................ ................................ ............................ 7 6. terms and definitions ................................ ................................ ................................ ................... 7 7. ordering information ................................ ................................ ................................ .................... 8 8. pin information ................................ ................................ ................................ .............................. 8 9. absolute maximum ratings ................................ ................................ ................................ ........ 11 10. recommended operating conditions ................................ ................................ ........................ 11 11. electrical characteristics ................................ ................................ ................................ ............ 12 12. typical characteristics ................................ ................................ ................................ ............... 21 13. functional description ................................ ................................ ................................ ................ 28 dc - dc buck converter ................................ ................................ ................................ ....... 32 13.1 switching frequency ................................ ................................ .............................. 32 13.1.1 operation modes and phase selection ................................ ................................ .. 33 13 .1.2 output voltage selection ................................ ................................ ........................ 33 13.1.3 soft start up ................................ ................................ ................................ ............ 34 13.1.4 c urrent limit ................................ ................................ ................................ ........... 34 13.1.5 ports description ................................ ................................ ................................ ................. 35 13.2 vddio ................................ ................................ ................................ ..................... 35 13.2.1 ic_en ................................ ................................ ................................ ..................... 35 13.2.2 nirq ................................ ................................ ................................ ........................ 35 13.2.3 gpio extender ................................ ................................ ................................ ........ 36 13.2.4 operating modes ................................ ................................ ................................ ................. 38 13.3 on mode ................................ ................................ ................................ ................. 38 13.3.1 off mode ................................ ................................ ................................ ............... 39 13.3.2 control interfaces ................................ ................................ ................................ ................ 40 13.4 4 - wire communication ................................ ................................ ......................... 40 13.4.1 2 - wire communication ................................ ................................ ......................... 44 13.4.2 details of the 2 - wire control bus protocol ................................ ............................. 45 13.4.3 internal temperature supervision ................................ ................................ ....................... 48 13.5 14. register definitions ................................ ................................ ................................ ..................... 49 register map ................................ ................................ ................................ ....................... 49 14.1 register definitions ................................ ................................ ................................ ............. 50 14.2 register page control ................................ ................................ ............................ 50 14.2.1 register page 0 ................................ ................................ ................................ ...... 50 14.2.2 register page 1 ................................ ................................ ................................ ...... 57 14.2.3
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 5 of 74 ? 2015 dialog semiconductor gmbh register page 2 ................................ ................................ ................................ ...... 64 14.2.4 15. ap plication information ................................ ................................ ................................ .............. 71 capacitor selection ................................ ................................ ................................ ............. 71 15.1 inductor selection ................................ ................................ ................................ ............... 71 15.2 16. package information ................................ ................................ ................................ ................... 73
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 6 of 74 ? 2015 dialog semiconductor gmbh figures figure 1: DA9211 system diagram ................................ ................................ ................................ ....... 2 figure 2: da9212 system diagram ................................ ................................ ................................ ....... 3 figure 4: connection diagram ................................ ................................ ................................ ............... 8 figure 5: 2 - wire bus timing ................................ ................................ ................................ .............. 18 figure 6: 4 - wire bus timing ................................ ................................ ................................ .............. 19 figure 32: interface of DA9211/12 with da9063 and the host processor ................................ ........... 28 figure 33: typical application of DA9211 ................................ ................................ ............................ 29 figure 34: typical application of da9212 ................................ ................................ ............................ 31 figure 3 5: concept of control of the bucks output voltage ................................ ................................ . 34 figure 36: gpio principle of operation (example paths) ................................ ................................ ..... 38 figure 37: schematic of 4 - wire and 2 - wire power manager bus ................................ .................. 41 figure 38: 4 - wire host write and read timing (ncs_pol = 0, cpol = 0, cpha = 0) ............. 42 figure 39: 4 - wire host write and read timing (ncs_pol= 0, cpol = 0, cpha = 1) .............. 42 figure 40: 4 - wire ho st write and read timing (ncs_pol = 0, cpol = 1, cpha = 0) ............. 43 figure 41: 4 - wire host write and read ttiming (ncs_pol = 0, cpol = 1, cpha = 1) ............ 43 figure 42: timing of 2 - wire start and stop condition ................................ ................................ 45 figure 43: 2 - wire byte write (sda line) ................................ ................................ .......................... 46 figure 44: examples of 2 - wire byte read (sda line) ................................ ................................ ..... 46 figure 45: examples of 2 - wire page read (sda line) ................................ ................................ .... 46 figure 46: 2 - wire page write (sda line) ................................ ................................ ......................... 47 figure 47: 2 - wire repeated write (sda line) ................................ ................................ .................. 47 figure 49: DA9211/12 wl - csp package outline drawing ................................ ................................ .. 73 tables table 1: ordering information ................................ ................................ ................................ ................ 8 table 2: pin description ................................ ................................ ................................ ......................... 9 tabl e 3: pin type definition ................................ ................................ ................................ .................. 10 table 4: absolute maximum ratings (note 1) ................................ ................................ ...................... 11 table 5: recommended operating conditions (note 1) ................................ ................................ ....... 11 table 6: buck converters characteristics ................................ ................................ ........................... 12 table 7: ic performance and supervision ................................ ................................ .......................... 15 table 8: digital i/o characteristics ................................ ................................ ................................ ...... 16 table 9: 2 - wire control bus characteristics ................................ ................................ ..................... 17 table 10: 4 - wire control bus characteristics ................................ ................................ ................... 19 table 11: graphs of typical characteristics ................................ ................................ ....................... 20 table 12: selection of the buck current limit from the coil parame ters ................................ ............... 35 table 13: 4 - wire clock configurations ................................ ................................ .............................. 41 table 14: 4 - wire interface summary ................................ ................................ ................................ 44 table 15: over - temperature thresholds ................................ ................................ .............................. 48 table 16: register map ................................ ................................ ................................ ....................... 49 table 17: recommended capacitor types ................................ ................................ ........................... 71 table 18: recommended inductor types ................................ ................................ ............................. 72
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 7 of 74 ? 2015 dialog semiconductor gmbh 5. revision h istory version date description 2.0 feb 2014 initial release 2.1 july 2014 updated transient line updated uvlo electrical characteristics swapped gpio0 and gpio1 updated ic_en electrical characteristics update osc_tune register updated quiescent current in pfm 2.2 november 2014 updated gpi0 - 4 , scl , sda v ih and v il specification updated ic_en description and timing relation to vdd_io updated use case 2 - phases update iq according to neroii - 34 fixed block diagrams assignment to DA9211 and da9212 added limitation on use of power good removed force pfm mode selection added minimum on time updated load and line transient performances updated quiescent curre nt in pwm 3.0 january 2015 added performance plots (to be done) updated iq added typical characteristics updated application information added power dissipation 6. terms and d efinitions ap application processor cpu central processing unit ddr double data rate sdram (synchronous dynamic random access memory) dvc dynamic voltage control gpu graphic processing unit ic integrated circuit otp one time programmable memory pcb printed circuit board pmic power management integrated circuit pol point of load
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 8 of 74 ? 2015 dialog semiconductor gmbh 7. ordering i nformation the order number consist s of the part number followed by a suffix indicating the packing method. for details, please consult the customer portal on the dialog web site or your local sales representative. table 1 : ordering i nformation part n umber package package d escription package o utline DA9211 - xx uu2 42 wl - csp t&r , 5000pcs figure 49 DA9211 - xxuu6 42 wl - csp waffle da9212 - xxuu2 42 wl - csp t&r , 5000pcs da9212 - xxuu6 42 wl - csp waffle 8. pin i nformation figure 4 : connection d iagram 1 2 3 4 5 6 7 a vdd_a1 vdd_a1 sda/ si scl/ sk gpi0/ trk vdd_b1 vdd_b1 a DA9211/12 b lx_a1 lx_a1 nc gpio2 gpi1/ clk_in lx_b1 lx_b1 b high power signals c vss_a1 vss_a1 fbap so/ gpio3 fbbp/ nc vss_b1 vss_b1 c high power noisy signals power signals d vss_a2 vss_a2 fban ncs/ gpi4 fbbn/ nc vss_b2 vss_b2 d noisy digital signals quasi static digital signals e lx_a2 lx_a2 vss vss_ana vddio lx_b2 lx_b2 e sensitive analog signals f vdd_a2 vdd_a2 nirq vsys ic_en vdd_b2 vdd_b2 f 1 2 3 4 5 6 7 42 balls s e e b a l l s t h r o u g h p a c k a g e
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 9 of 74 ? 2015 dialog semiconductor gmbh table 2 : pin d escription pin name signal name second function type ( see table 3 ) description b1, b2 lx_a1 ao switching node for buck a phase 1 e1, e2 lx_a2 ao switching node for buck a phase 2 b6, b7 lx_b1 ao switching node for buck b phase 1 e6, e7 lx_b2 ao switching node for buck b phase 2 a1, a2 vdd_a1 ps supply voltage for buck a phase 1 to be connected to vsys f1, f2 vdd_a2 ps supply voltage for buck a phase 2 to be connected to vsys a6, a7 vdd_b1 ps supply voltage for buck b phase 1 to be connected to vsys f6, f7 vdd_b2 ps supply voltage for buck b phase 2 to be connected to vsys f5 ic_en di i ntegrated c ircuit (ic) enable signal f3 nirq do i nterrupt line towards the host e5 vdd io ps i/o voltage rail c3 fb ap ai positive sense node for the b uck a d3 fban ai negative sense node for the b uck a c5 fbbp ai positive sense node for the buck b for da9212 n/c ai for DA9211 d5 fbbn ai negative sense node for the buck b for da9212 n/c ai for DA9211 a5 gpi 0 trk di /ai general purpose input , input track b5 gpi1 clk_in di general purpose input , digital clock input b4 gpio2 di o general purpose input /output a3 sda si dio 2 - wire d ata , 4 - wire data input/output a4 scl sk di 2 - wire c lock , 4 - wire clock d4 ncs gpi4 di 4 - wire chip select, general purpose input c4 s o gpio3 dio 4 - wire data output, general purpose input/output b3 nc leave floating f4 vsys ps supply for ic and input for voltage supervision e3 vss vss e4 vss_ana vss
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 10 of 74 ? 2015 dialog semiconductor gmbh pin name signal name second function type ( see table 3 ) description c1, c2 d1, d2 c6, c7 d6, d7 vss_a1, vss_a2 vss_b1 vss_b2 vss connect together table 3 : pin t ype d efinition pin t ype description pin t ype description di digital input ai analog ue input do digital output ao analog ue output dio digital input/output aio analog ue input/output ps power supply vss ground
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 11 of 74 ? 2015 dialog semiconductor gmbh 9. absolute maximum ratings table 4 : absolute maximum ratings ( note 1 ) symbol parameter conditions min typ max unit t stg s torage temperature - 65 +165 c t a _ lim l imiting ambient temperature - 40 +85 c v dd _ lim l imiting supply voltage - 0.3 5.5 v v pin l imiting voltage at all pins except above - 0.3 v dd + 0.3 (max 5.5) v p tot total power dissipation ( note 2 ) d erating factor above t a = 70c: 23 mw/c 1265 1610 mw v esd _ hbm e lectrostatic discharge voltage human b ody m odel 2 kv note 1 stresses beyond those listed under absolute m aximum r atings may cause permanent damage to the device. these are stress ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2 obtained from simulation on a 2s2p 4l jedec board (eia/jesd51 - 2) . influenced by pcb technology and layout 10. recommended operating conditions table 5 : recommended operating conditions ( note 1 ) symbol parameter conditions min typ max unit v dd s upply voltage 2.8 5.5 v v ddio i nput/output supply voltage 1.2 3.6 ( note 2 ) v note 1 within the specified limits, a life time of 10 years is guaranteed note 2 v ddio is not allowed to be higher than v dd
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 12 of 74 ? 2015 dialog semiconductor gmbh 11. electrical characteristics table 6 : buck converters characteristics unless otherwise noted, the following is valid for t a = - 40 to +85 oc, v dd = 2.8 v to 5.5 v, c out = 22 f /phase , local sensing symbol parameter conditions min typ max unit v dd s upply voltage v dd _ x = v sys 2.8 5.5 v c out o utput capaci tance (per phase) i ncluding voltage and temperature coefficient 11 22 28.6 f 23 47 61 f esr cout equivalent series resistance (per phase) f > 100 khz 10 m? phase047 inductance (per phase) i ncluding current and temperature dependence 0.23 0.47 0.62 h l phase022 inductance (per phase) i ncluding current and temperature dependence 0.11 0.22 0.29 h dcr l phase inductor resistance 30 100 m? buck buck o utput voltage ( note 1 ) i o = 0 to i o_m ax 0.3 1.57 v v oacc o utput voltage accu r acy pwm mode i ncl. static line/load reg and voltage ripple v buck 1 buck < 1 v 20 mv v buck = 1 v v dd = 3.8 v no load - 1.0 +1.0 % v buck = 1 v v dd = 3.8 v no load t a = 27 oc - 0.5 +0.5 % v tr_ loa d load regulation transient voltage i o = 0 to 5 a, 10 a/s 4 - phase operation , pwm v buck buck < 1 v - 3 - 30 mv note 2 +3 +30 mv % i o = 0 to 5 a, 10 a/s phase shedding, pwm v dd buck buck < 1 v - 3 . 5 - 35 mv note 2 +3 . 5 +35 mv %
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 13 of 74 ? 2015 dialog semiconductor gmbh symbol parameter conditions min typ max unit i o = 0 to 5 a, 10 a/s auto mode, ph shedding c out = 47 f v buck 1 v 0.6 v v buck < 1 v - 3 .5 - 35 mv note 2 +3 .5 +35 mv % v tr _line line regulation transient voltage v dd = 3 to .3.6 v dt =10 s i o = i o(m ax ) /2 8 mv r rs_max maximum remote sensing resistance ( note 3 ) t o sense connection at point of load 10 m? l rs_max maximum remote sensing inductance ( note 3 ) t o sense connection at point of load 10 nh i o_ max maximum output current per phase 3 000 ma i lim_ min minimum current limit per phase (programmable) bucka_ilim buckb_ilim = 00 0 0 - 20% 2000 20% ma i lim_max maximum current limit per phase (programmable) bucka_ilim buckb_ilim = 1111 - 2 0% 50 00 20% ma i q _pwm quiescent current @ synchronous rectification mode per phase no load v dd = 3.7 v 10 ma f sw s witching frequency 3 mhz t on_min minimum on time 20 ns t stup start up time bucka_up_ctrl b uckb _up_ctrl = 01 1 50 ( note 4 ) s r o_pd output pull - down resistance for each phase at the lx node @0.5 v, (see buckx_pd_dis ) 150 200 ? pfm mode v buck _pfm buck output voltage in pfm i o = 0 ma to i o_m ax 0.3 1.57 v i q _ pfm _a2 da9212 quiescent current buck a enabled no load v dd = 3.7 v 56 a i q _ pfm _a4 DA9211 quiescent current buck enabled no load v dd = 3.7 v 70 a
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 14 of 74 ? 2015 dialog semiconductor gmbh symbol parameter conditions min typ max unit i q _ pfm _a2b2 da9212 quiescent current buck a enabled buck b enabled no load v dd = 3.7 v 10 4 a note 1 programmable in 10 mv increments note 2 additionally to the dc accuracy. the value is intended measured directly at c out(ext) . in case of remote sensing, parasitics of pcb and external components may affect this value. note 3 (ca 13 cm) trace routed over a ground plane (approx 1.2 nh/cm) note 4 time from begin to end of the voltage ramp. additional 10 s typical delay, plus internal sync to the enabl e port
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 15 of 74 ? 2015 dialog semiconductor gmbh table 7 : ic performance and supervision t a = - 40 to +85 oc symbol parameter conditions min typ max unit i dd_off o ff state supply current @vsys,vddx ic_en = 0 t a = 27 c 0.1 1 a i dd _ on o n state supply current @vsys,vddx ic_en = 1 buck a/b off t a = 27 c 12 a v th_ p g p ower good threshold voltage referred to v buck - 50 m v v hys_pg p ower good hysteresis voltage 50 mv v th _uvlo_ vdd u nder voltage lockout threshold @ v dd 2.0 v v th _ u v lo _ io u nder voltage lockout threshold @ vddio 1.35 1.45 1.55 v v hys_uvlo_ io u nder voltage lockout hysteresis @ vddio 7 0 mv t th_ warn t hermal warning threshold temperature 110 125 140 c t th_crit t hermal critical threshold temperature 125 140 155 oc t th_por t hermal power on reset threshold temperature 135 150 165 c f osc i nternal oscillator frequency - 7 % 6.0 + 7 % mhz
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 16 of 74 ? 2015 dialog semiconductor gmbh table 8 : digital i/o c haracteristics t a = - 40 to +85 oc symbol parameter conditions min typ max unit v ih _en high level input voltage @ pin ic_en 0.7* v ddio v v il _en low level input voltage @ pin ic_en 0.3* v ddio v t en e nable time i/f operating 750 s r o_ p u _ gpo p ull up resistor @ gpo v ddio = 1.8 v v gp o = 0v 100 k ? i_ p d _gpi p ull down resistor @ gpi v ddio = 1.8v v gpi = v ddio 150 k ? ih gpi0 - 4 , scl , s da, (2 - wire m ode) high level input voltage v ldo core m ode v ddio m ode 1.75 0.7* v ddio v v il gpi0 - 4 , scl , s da, (2 - wire m ode) low level input voltage v ldocore m ode v ddio m ode 0.75 0.3* v ddio v v ih _4wire sk, ncs, si (4 - wire mode) high level input voltage 0.7* v ddio v v il _ 4wire sk, ncs, si (4 - wire mode) low level input voltage 0.3* v ddio v v oh gpo 2 - 3 , so (4 - wire m ode) high level output voltage p ush - pull m ode @1ma v ddio ddio v v ol1 gpo2 - 3, sda (2 - wire mode) so (4 - wire m ode) low level output voltage @ i ol = 1 ma 0.3 v v ol3 s da (2 - wire mode) low level output voltage @ i ol = 3 ma 0.24 v v ol20 s da (2 - wire mode) low level output voltage @ i ol = 20 ma 0.4 v c in clk, s da (2 - wire mode) i nput c apacitance 2.5 10 pf
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 17 of 74 ? 2015 dialog semiconductor gmbh symbol parameter conditions min typ max unit t sp clk, s da (2 - wire mode) spike suppression pulse width fast/fast+ mode high speed mode 0 0 50 10 ns t fda f all time of sda signal (2 - wire mode) fast @ cb<550pf hs @ 10 DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 18 of 74 ? 2015 dialog semiconductor gmbh symbol parameter conditions min typ max unit t f _ hs f all time @ pin clk and data i nput requirement 160 ns t su_d_hs d ata set - up time 10 ns t h_d_ hs d ata hold time 0 ns t su _ sto _ hs stop condition set - up time 160 ns note 1 minimum clock frequency is 10 khz if 2wire_to is enabled figure 5 : 2 - wire bus timing
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 19 of 74 ? 2015 dialog semiconductor gmbh table 10 : 4 - wire control bus characteristics t a = - 40 to +85 oc symbol parameter label in plot min typ max unit c b b us line capacitive load 100 pf t c c ycle time 1 70 ns t su_ c s c hip select setup time 2, from cs active to first sk edge 20 ns t h_ c s c hip select hold time 3, from last sk edge to cs idle 20 ns t w_ cl c lock low duration 4 0.4 x t c ns t w_ch c lock high duration 5 0.4 x t c ns t su_ si d ata input setup time 6 10 ns t h _si d ata input hold time 7 10 ns t v _ so d ata output valid time 8 22 ns t h_ so d ata output hold time 9 6 ns t w_ cs c hip select high duration 1 0 20 ns figure 6 : 4 - wire bus timing s k s i ( 2 ) t s u _ c s n c s s o 7 0 % 3 0 % 7 0 % 3 0 % ( 6 ) t s u _ s i 7 0 % 3 0 % ( 7 ) t h _ s i 7 0 % 3 0 % ( 8 ) t v _ s o ( 9 ) t h _ s o ( 3 ) t h _ c s ( 1 0 ) t w _ c s ( 5 ) t w _ c h ( 4 ) t w _ c l ( 1 ) t c
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 20 of 74 ? 2015 dialog semiconductor gmbh table 11 : graphs of typical characteristics patameter test conditions figure efficiency efficiency vs output current, v out = 1.0 v , 4 phases figure 7 efficiency vs output current, v out = 1.2 v , 4 phases figure 8 efficiency vs output current, v out = 0.9 v , 4 phases figure 9 efficiency vs outpu t current, v out = 1.0 v , 2 phases figure 10 efficiency vs output current, v out = 1.2 v , 2 phases figure 11 efficiency vs outpu t current, v out = 0.9 v , 2 phases figure 12 efficiency vs input voltage, i out = 100 ma figure 13 efficiency vs input voltage, i out = 2 a figure 14 efficiency vs input voltage, i out = 10 a figure 15 start - up no load, startup_ctrl=0 00 (slowest), v dd =3. 7 v, v out =1.0 v figure 16 no load, startup_ctrl=1 00 ( default ), v dd =3. 7 v, v out =1.0 v figure 17 no load, startup_ctrl=11 0 ( fastest ), v dd =3. 7 v, v out =1.0 v figure 18 1 ? dd =3. 7 v, v out =1.0 v figure 19 1 ? dd =3. 7 v, v out =1.0 v figure 20 1 ? dd =3. 7 v, v out =1.0 v figure 21 start up fr om ic_en no load, startup_ctrl=100 (default), v dd =3.7v, v out =1.0v figure 22 dvc dvc no load, slowest speed 2.5mv/s, dd =3.7v, v out 1.2v/0.8v figure 23 dvc no load, default speed 10mv/s, dd =3.7v, v out 1.2v/0.8v figure 24 dvc no load, fastest speed 20mv/s, dd =3.7v, v out 1.2v/0.8v figure 25 switching waveforms pwm, no load, v dd =3. 7 v, v out =1.0 v figure 26 voltage and current ripple, pwm, no load, v dd =3. 7 v, v out =1.0 v figure 27 pfm, no load, v dd =3. 7 v, v out =1.0 v figure 28 load transient response pwm, 4 - phases, 0 ? in 10 a/s, v dd =3.7 v, v out =1.0 v figure 29 pwm, 4 - phases, 1 ? in 10 a/s, v dd =3.7 v, v out =1.0 v figure 30 auto , 4 - phases, 10ma ? in 10 a/s, v dd =3.7 v, v out =1.0 v figure 31
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 21 of 7 4 ? 2015 dialog semiconductor gmbh 12. typical characteristics figure 7 figure 8 figure 9 figure 10
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 22 of 74 ? 2015 dialog semiconductor gmbh figure 11 figure 12 figure 13 figure 14
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 23 of 74 ? 2015 dialog semiconductor gmbh start up n o load, startup_ctrl=000 (slowest) v dd =3.7v, v out =1.0 v figure 15 figure 16 start up n o load, startup_ctrl= 1 00 ( default ) v dd =3.7v, v out =1.0 v start up n o load, startup_ctrl= 11 0 ( fastest ) v dd =3.7v, v out =1.0 v figure 17 figure 18
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 24 of 74 ? 2015 dialog semiconductor gmbh start up 1 ? load , startup_ctrl=000 (slowest) v dd =3.7v, v out =1.0 v start up 1 ? load , startup_ctrl= 1 00 ( default ) v dd =3.7v, v out =1.0 v figure 19 figure 20 start up 1 ? load , startup_ctrl= 11 0 ( fastest ) v dd =3.7v, v out =1.0 v start up from ic_en no l oad, startup_ctrl=100 (d efault) v dd =3.7v, v out =1.0 v figure 21 figure 22
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 25 of 74 ? 2015 dialog semiconductor gmbh dvc n o load, slowest speed 2.5mv/ s v dd =3.7v, v out 1.2v/0.8v dvc no load , default speed 10mv/ s v dd =3.7v, v out 1.2v/0.8v figure 23 figure 24 dvc n o load, fastest speed 20mv/ s v dd =3.7v, v out 1.2v/0.8v switching waveforms, pwm , no load v dd =3.7v, v out = 1.0v figure 25 figure 26
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 26 of 74 ? 2015 dialog semiconductor gmbh voltage and current ripple, pwm , no load v dd =3.7v, v out = 1.0v switching waveforms, pfm , no load v dd =3.7v, v out = 1.0v figure 27 figure 28 transient load , pwm, 4 - phases 0 ? 5a in 10a/ s, v dd =3.7 v, v out =1.0 v transient load , pwm, 4 - phases 1 ? 5a in 10a/ s, v dd =3.7 v, v out =1.0 v figure 29 figure 30
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 27 of 74 ? 2015 dialog semiconductor gmbh transient load , auto , 4 - phases 1 0ma ? 5a in 10a/ s, v dd =3.7 v, v out =1.0 v figure 31
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 28 of 74 ? 2015 dialog semiconductor gmbh 13. functional d escription flexible configurability and the availability of different control schemes make both DA9211 and da9212 the ideal single/d ual buck companion ic s to expand the existing capabilit ies of a master pmic. due to the advanced compatibility between both DA9211 and da9212 and the da9063, they offer several advantages when they are operated together . these ad vantages include : DA9211 and da9212 can be enabled and controlled by da9063 during the power up sequence, thanks to da9063s dedicated output signals during power - up , and compatible input controls in both DA9211 and da9212 . DA9211 and da9212 can be used in a completely transparent way for the host processor and can share the same control interface (same spi chip select or i2c address), thanks to the compatible registers map. DA9211 and da9212 has a dedicated register space for configuration and control which doesnt conflict with da9063. DA9211 and da9212 supports a power - good configurable port for enhanced communication to the host processor and improved power - up sequencing. DA9211 and da9212 can both share the same interrupt line with da9063 . in addition, the 2 - wire / 4 - wire interfaces allow DA9211 and da9212 to fit to many standard pmu parts and power applications. figure 32 : interface of DA9211/12 with da9063 and the host processor d a 9 0 6 3 h o s t p r o c e s s o r n i r q n o n k e y n r e s e t v d d v c h a r g e r n s h u t d o w n g p i o s o u t _ 3 2 k c o n t r o l i f d a 9 2 1 1 / 1 2 g p i o 2 ( a c _ o k ) c o n t r o l i f g p i o 9 n i r q p w r 1 _ e n n o f f l i d g p i 0 ( e n a b l e ) i c _ e n p w r _ e n s y s _ e n g p i 1 ( v o l t a g e s e t )
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 29 of 74 ? 2015 dialog semiconductor gmbh as shown in figure 32 , a typical application case includes a host processor, a main pmic ( for example, da9063) and DA9211 or da9212 used as companion ic for the high power core supply. t he easiest way of controlling DA9211 and da9212 is through the control interface. the master initiating the communication must always be the host processor that reads and writes to the main pmic , and to the DA9211 and da9212 registers. to poll the status of DA9211 or da9212, the host processor must access the dedicated register area through the control interface. DA9211 and da9212 can be additionally controlled by means of hardware inputs. figure 33 : typical application of DA9211 v d d _ a 1 v s y s v s s _ a n a v i n l x _ a 1 f b a p f b a n a c _ o k ( g p i o 2 ) p o w e r g o o d ( g p i o 3 ) d a 9 2 1 1 c p u / g p u / d d r c o r e e n ( g p i 0 ) v s e l ( g p i 1 ) n i r q s c l s d a v d d i o v c h a r g e r e x t s u p p l y d a 9 0 6 3 ( p m i c ) s e n s e + s e n s e - v d d i o i 2 c _ a d d r _ s e l ( g p i 4 ) l p _ m o d e i c _ e n g p i o 9 ( s e q ) v d d _ a 2 v d d _ b 1 v d d _ b 2 l x _ a 2 l x _ b 1 l x _ b 2
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 30 of 74 ? 2015 dialog semiconductor gmbh figure 33 shows a typical use case of DA9211 for the supply of cpu, gpu , or ddr rails. the ic is en abled and disabled by the main pmic via ic_en port as part of its sequencer. once the ic is enabled, the core application processor enables the buck converter with the en1 signal and manages the output voltage selection with the vsel signal. the vsel signal can be shared between the main pmic and the DA9211 . three gpi/ gpios embedded in DA9211 are used in this case : gpi o2 signals the insertion of an external charger in the application (through interrupt to the host processor) gpi o3 indicat es a power - good - condition , either to proceed with the power up sequence or to enable an external supply connected to the port gpi4 is used for t he i2c interface address hardware selection
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 31 of 74 ? 2015 dialog semiconductor gmbh figure 34 : typical application of da9212 figure 34 shows a typical use case of da9212 for the simultaneous supply of a cpu and a gpu rail. the core application processor enables and disables the ic, the cpu and the gpu individually via dedicated ports on da9212 . v d d _ a 1 v s y s v s s _ a n a v i n l x _ a 1 f b a p f b a n f b b p f b b n s e n s e + s e n s e - d a 9 2 1 2 c p u g p u c o r e e n _ a ( g p i 0 ) e n _ b ( g p i 1 ) n i r q s c l s d a v d d i o s e n s e + s e n s e - i 2 c _ a d d r _ s e l ( g p i 4 ) v d d i o i c _ e n v d d _ a 2 v d d _ b 1 v d d _ b 2 l x _ a 2 l x _ b 1 l x _ b 2
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 32 of 74 ? 2015 dialog semiconductor gmbh dc - dc buck converter 13.1 DA9211 is a four - phas e 12 a high efficiency synchronous step - down dvc regulator, operating at a high frequency of typically 3 mhz . it supplies an output voltage of typically 1.0 v for a cpu rail, configura ble in the range 0.3 C 1.57 v, with high accuracy in steps of 10 mv. da9212 contains two buck converters, b uck a and b uck b , each capable of delivering 6 a to improve the accuracy of the delivered vo ltage, e ach buck converter is able to support a differential sensing of the configured voltage directly at the point of load via dedicated positive and negative sense pin s . both b uck a and b uck b ha ve two voltage registers each . o ne defin es the normal output voltage , while the other offer s an alternative retention voltage . in this way different application power modes can easily be supported. th e voltage selection can be operated either via gpi or via control interface to guarantee the maximum flexibility according to the specific host processor status in the application. when a buck is enabled, its output voltage is monitored and a power - good signal indicates that the buck output voltage has reached a level higher than the v th(p g ) threshold. the power - good is lost when the voltage drops below v th(p g ) - v hys(pg) , which is the level at which the signal is de - asserted. the power good s ignalling should not be used in conjunction with fast start up rates, configured in buckx_up_ctrl register fields and can be individually masked during dvc transitions using the pga_dvc_mask and pgb_dvc_mask bits. for each of the buck converters the status of the power - good in dicator can be read back via i2c from the pwrgood_a and pwrgood_b status bit s . it can be also individually assigned to either gpio2 or gpio3 using bucka_pg_sel and buckb_pg_sel . for correct functionality , the gpio ports need to be configured as output. an i2c write i n gpiox_mode can overwrite the internal configu ration so that a new update will be automatically done only when the internal power - good indicator changes status. the buck converters are capable of supporting dvc transition s that occur: when the active and selected a - voltage or b - voltage i s updated to a new target value. when the voltage selection is changed from the a - voltage to the b - voltage ( or b - voltage to the a - voltage) using vbucka_sel and vbuckb_sel . the dvc controller operates in pulse width modulation ( pwm ) mode with synchronous rectification. when the host processor changes the output voltage, the voltage transition of each buck converter can be individually signalled with a ready signal routed to either gpio2 or gpio3. the port has to be configured as gpo and selecte d for the functionality via readya_conf or readyb_conf . in contrast to the power - good signal, the ready only informs the host processor about the completion of the digital dvc ramp without confirming that the target voltage has actually been reached. the slew rate of the dvc transition is individually programmed for each buck converter at 10mv per (4, 2, 1 or 0.5 s) via control bit slew_rate_a and slew_rate_b . the typical supply current is in the order of 8 ma per phase (quiescent current and charge/discharge current) and drops to <1 a when the buck is turned off. when the buck is disabled , a pull - down resistor ( typical ly 150 ? ) for each phase is activated depending of the value stored in register bit s bucka_pd_dis and buckb_pd_dis . phases disabled using phase_sel_a and phase_sel_b will not have any pull - down. the pull - down resistor is always disable d at all phases when DA9211 and da9212 are off. switching frequency 13.1.1 the switching frequency is chosen to be high enough to allow the use of a small 0.47 h inductor (see a complete list of coils in the application information section (see section 15 ). the buck
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 33 of 74 ? 2015 dialog semiconductor gmbh switching frequency can be tuned using register bit osc_tune . the internal 6 mhz oscillator frequency is tuned in steps of 180 khz. this impacts the buck converter frequency in steps of 90 khz and helps to mitigate possible disturbances to other hf systems in the application. operation modes and phase selection 13.1.2 the buck converters can operate in synchronous pwm mode and pfm mode. the operating mode is selected using register bits bucka_mode and buck b _mode . an automatic phase shedding can be enabled for each buck converter in pwm mode via ph_sh_en_a , ph_sh_en_b , thereby automatically reducing or increasing the number of active phases depending on the output load current. for da921 2 the phase shedding will automatically change between 1 - phase and 2 - phase operation at a typical current of 1.3 a . for DA9211 the phase shedding will automatically change between 1 - phase and 4 - phase operatio n at a typical current of 1.6 a . the phase_sel_a and phase_sel_b register field s limit the maximum number of active phases under any conditions . if the automatic operation mode is selected on bucka_mode or buck b _mode , the buck converters will automatically change between synchronous pwm mode and pfm depending on the load current. this improves the efficiency of the converters across the whole range of out put load currents. output voltage selection 13.1.3 the switching converter can be configured using either a 2 - wire or a 4 - wire interface. for security reasons , the re - programming of registers that can cause damage when wrongly programmed ( for example, the voltage settings) can be disabled by asserting the control v_lock . when v_lock is asserted, reprogramming the register s 0xd0 to 0x14f from control interfaces is disabled . for each buck converter two output voltages can be pre - configured inside registers vbucka_a and vbuck b _ a , and registers vbucka_ b and vbuck b _ b . the output voltage can be selected by either toggling register bit s vbucka_sel and vbuckb_sel or by re - programming th e selected voltage control register. both changes will result into ramped voltage transitions , during which the ready signal is asserted . after being enabled, the buck converter will by default use the register settings in vbucka_a and vbuck b _ a unless the output voltage selection is configured via the gpi port. if 00 has been selected in bucka_mode or buck b _mode , a - /b - voltage selection registers vbuckx_x control the operation of th e pwm and pfm modes. regardless of the values programmed in the vbuckx_a and vbuckx_b registers, t he register s vbucka_max , vbuck b _max will individually limit the output voltage that can be set for each of the buck converters . the buck converter provides an optional hardware enable/disable via selectable gpi, and configured via control register bits bucka_gpi and buckb_gpi . a change of the output voltage from the state of a gpi is enabled via control register bits vbucka_gpi and vbuckb_gpi . after detecting a rising or falling edge at the related gpis, DA9211 and da9212 will configure the buck converters according to their status . in addition to selecting between the a/b voltages, a track mode can be activated for b uck a to se t the output voltage . in the DA9211 , the track mode is applied to the 4 - phase buck converter. this feature can be enabled on gpi0 via gpi0_pin . t he output voltage will be configured to follow the value applied at a s elected gpi pin. the voltage applied at gpi 0 must be in the same range as the nominal output voltage selectable for the buck rail (see vbucka_a and vbucka_ b regist ers). in t rack m ode , only single ended remote sensing is possible .
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 34 of 74 ? 2015 dialog semiconductor gmbh in t rack m ode , the content of the vbucka_sel bit is ignored, as well as vbucka_a and vbucka_ b bits . they will be come active again once the voltage track mode is disabl ed. the gpi0 does not generate any event in this case. figure 35 : concept of control of the buck s output voltage s oft start up 13.1.4 to limit in - rush current from vsys , the buck converter s can perform a soft - start after being enabled . the start - up behaviour is a compromise between acceptable inrush current from the battery and turn - on time. in DA9211 and da9212 , different ramp times can be individually configured for each buck converter on register bucka_up_ctrl and b uckb _up_ctrl . rates higher than 20 mv/s may produce overshoot during the start - up phase, so they should be considered carefully. a ramped power - down can be selected on register bit s bucka_down_ctrl and buck b _down_ctrl . when no ramp is selected, the output node will be discharged only by the pull - down resistor, if enabled via bucka_pd_dis and buckb_pd_dis . current limit 13.1.5 the integrated current limit is meant to protect DA9211 and da9212 s power stages and the external coil from excessive current. the buck s current limit should be configured to be at least 40% higher than the required maximum continuous output current (see table below) . when reaching the current limit, each buck converter generates an event and an interrupt to the host processor unless the interrupt has been masked using the ocx_mask controls. the se oca_mask and ocb_mask control bits can be used to mask the generation of over - current events during dvc transitions. an extra maski ng time as defined in ocx_mask will be automatically added to the dvc interval after the dvc has finished in order to ensure that the possible high current levels needed for dvc do not influence the event generation .
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 35 of 74 ? 2015 dialog semiconductor gmbh table 12 : selec tion of the buck current limit from the coil parameters min isat (ma) frequency (mhz) buck current limit (ma) average current (ma) 5060 3 4600 3300 4180 3 3800 2700 3080 3 2800 2000 1760 3 1600 1100 ports description 13.2 th is section describes the functionality of each input / output port . vddio 13.2.1 vddio is an independ e nt io supply rail input to DA9211 and da9212 that can be assigned to the power manager interface and to the gpios (see control pm_if_v and gpi_v ). the rail assignment deter mines the io voltage levels and logical thresholds (see also the digital i/o characteristics in table 8 ). an integrated under voltage lockout circuit f or the vddio prevents internal errors by disabling the i2c communication when the voltage drops below v ulo_io . in that case the buck converters are also disabled and can not be re - enabled (even via input port) until the vddio under - voltage condition has be en resolved . at the exit of the vddio under voltage condition an event e_uvlo_io is generated and the nirq line is driven active if the event is not m asked. the vddio under - voltage circuit monitors voltages relative to a nominal voltage of 1.8v . if a different rail voltage is being used , the under - voltage circuit can be disabled via uvlo_io_dis . note that the maximum speed at 4 - wire interface is only available if the selected supply rail is greater than 1.6 v. ic_en 13.2.2 ic_en is a general enable signal for DA9211 and da9212 , turning on and off the internal circuitry ( for example, the reference, the digital core, etc). correct control of this port has a direct impact on the quiescent current of the whole application . a low level of ic_en allow s the device to rea ch the minimum quiescent current. the voltage at this pin is continuously sensed by a dedicated analogue circuit. the host processor will be allowed to start the communication with DA9211 and da9212 through the control interface and , for example to turn on the buck converter s , a delay time of t en after assertion of the ic_en pin . if the buck s are enabled via otp (see bucka_en and buckb_en control s ), they will start up auto matically after assertion of ic_en . the ic_en signal shall be asserted and deasserted only when the vdd_io supply is available and its level is above the undervoltage threshold level v th _ u v lo _ io . nirq 13.2.3 the nirq port indicates that an interrupt - causing event has occurred and that the event/status information is available in the related registers. the nirq is an output signal that can either be
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 36 of 74 ? 2015 dialog semiconductor gmbh push - pull or open drain (selected via irq_type ). if an active high irq signal is required , it can be achieved by asserting control irq_level (r ecommended for push - pull mode). examples of this type of information can be critical temperature and voltage, fault conditions, status changes at gpi ports, and so forth . the event registers hold information about the events that have occurred. events are triggered by a status change at the monitored signals. when an event bit is set , the nirq signal is asserted unless this interrupt is masked by a bit in the irq mask register. the nirq will not be released until all event registers with asserte d bits have been read and cleared. new events that occur during reading an event register are held until the event register has been cleared, ensuring that the host processor does not miss them. gpio extender 13.2.4 DA9211 and da9212 i ncludes a gpio extender that offers up to five 5 v - tolerant general purpose input/output ports . e ach port is ontrolled via registers from the host processor. the gpio 3 and gpi 4 ports are pin - shared with the 4 - wire control interface. for instance, if gpio3_pin = 01, gpi4_pin = 01 (interface selected), the gpio 3 and gpi 4 ports will be exclusively dedicated to output and chip - select signaling for 4 - wire purposes. i f the alternative function is selected, all gpios c onfiguration as per registers 0x58 to 0x5a and 0x145 will be ignored. gpis are supplied from the internal rail vddcore or vddio (selected via gpi_v ) an d can be configured to be active high or active low (selected via gpiox_type). the input signals can be debounced or directly change the state of the assigned status register gpix to high or low, according to the setting of gpiox_mode. the debouncing time is configurable via control debounce (10 ms default). when ever the status has changed to its configured active state (edge sensitive) , the assigned e vent register is set and the nirq signal is asserted (unless this nirq is masked, see also figure 36 ). whenever DA9211 and da9212 is enabled and enters on mode (also when enabled changing the setting of gpiox_pin) the gpi status bits are initiated towards their configured passive state. this ens ures that already active signals are detected , and that they create an event imm ediately after the gpi comparators are enabled. the buck enable signal (buckx_en) can be controlled directly via a gpi, if so configured in the bucka_gpi and buckb_gpi reg ister s . if it i s required that gpi ports do not generate an event when configured for the hw control of the switching regulator, the relative mask bit should be set. gpis can alternatively be selected to toggle the vbucka_sel and vbuckb_sel from rising and falling edges at this inputs. apart from changing the regulator output voltage this also provides hardware control of the regulator mode (normal/low power mode) from the settings of error! eference source not found. , error! reference source not found. , error! reference source not foun d. , and error! reference source not found. (enabled if bucka_mode or buck b _mode = 00). all gpi ports have the additional option of activating a 100 k? pull - down resistor via gpiox_pupd, which ens ures a well defined level in case the input is not actively driven. if e nabled via addr_sel_conf , the i2c address selection can be assigned to a specific gpi. an active voltage level at the selected gpi configures the slav e address of DA9211 and da9212 to if_base_addr 1 whil e a passive voltage level configures the slave address to if_base_addr 2 . if no gpi is selected then the if_base_addr 1 is automatically used. if defined as an output , gpios can be configured to be open - drain or push - pull. if configured as push - pull, the supply rail is vddio . by disabling the internal 120 k? pull - up resistor in open - drain mode , the gpo can al so be supplied from an external rail. the output state will be assigned as configured by the gpio register bit gpiox_mode.
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 37 of 74 ? 2015 dialog semiconductor gmbh a specific power - good port for each of the buck converters can be configured via bucka_pg_sel and buckb_pg_sel . the re spec tive port must be configured as gpo for correct operation. if assigned to the same gpo, it i s necessary that the power - good indicators for b uck a and b uck b are both active (supply voltages in range) to assert the overall power - good . the signal will be released as soon as one of the single power - good signals is not active ( that is, at least one supply is out of range). the power good signalling should not be used in conjunction wi th fast start up rates, configured in buckx_up_ctrl register fields. whenever the gpio unit is off (por or off mode) all ports are configured as open drain active high (pass device switched off, high impedance state). when leaving por the pull - up or pull - d own resistors will be configured from register gpiox_pupd .
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 38 of 74 ? 2015 dialog semiconductor gmbh figure 36 : gpio principle of operation (example paths) operating modes 13.3 on mode 13.3.1 DA9211 and da9212 is in on mode when the ic_en port is higher than en_on and the supply voltage is higher than v th(uvlo)( vdd ) . once enabled, the host processor can start the communication with DA9211 and da9212 via control interface after the t en delay needed for internal circuit start up. if bucka_en or buckb_en is asserted when DA9211 and da9212 is in on mo de the power up of the related buck converter is initiated. if the bucks are controlled via gpi, the level of the controlling ports is checked when entering on mode, so that an active level will immediately have effect on the i n p u t r e f e r e n c e b u f f e r g p i 0 _ p i n i n t e r r u p t m a s k : m _ g p i 0 r i s i n g o r f a l l i n g e d g e g p i o 0 _ t y p e : a c t i v e h i g h / l o w g p i 0 s t a t u s r e g i s t e r n i r q e _ g p i 0 e v e n t r e g i s t e r r e s e t e v e n t r e g i s t e r w r i t e 1 0 0 k . . . n o r n o r g p i o 0 _ p u p d g p i b u c k g p i o 3 _ p i n r e g u l a t o r c o n f i g u r e b u c k h w c o n t r o l b u c k _ e n v b u c k _ s e l d e b o u n c e g p i 0 _ m o d e : d e b o u n c e o n / o f f i n t e r r u p t m a s k : m _ g p i 3 r i s i n g o r f a l l i n g e d g e g p i o 3 _ t y p e : a c t i v e h i g h / l o w g p i 3 s t a t u s r e g i s t e r e _ g p i 3 e v e n t r e g i s t e r r e s e t e v e n t r e g i s t e r w r i t e 1 0 0 k v d d _ i o 1 2 0 k g p o ( o p e n d r a i n ) g p o ( p u s h - p u l l ) g p o 3 _ m o d e : 0 o r 1 n o r g p i o 3 _ p u p d g p i o 3 _ p u p d v d d _ i o g p i d e b o u n c e g p i o 3 _ m o d e : d e b o u n c e o n / o f f v d d _ i o 4 - w i r e s o r e a d y s i g n a l a s s e r t e d d u r i n g d v c r e a d y _ e n t r a c k m o d e i n t e r f a c e r e s e r v e d r e s e r v e d
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 39 of 74 ? 2015 dialog semiconductor gmbh buck. if bucka_en or buckb_en are not asserted and all controlling gpi port s are in active, the buck converter will stay off with the output pull - down resistor enabled/disabled according to the setting of bucka_pd_dis and buckb_pd_dis . off mode 13.3.2 DA9211 and da9212 is in off mode when the ic_en port is lower than en_off. in off mode, the bucks are always disabled and the output pull - down resistors are disabled independently of bucka_pd_dis and buckb_pd_dis . all i/o ports of DA9211 and da9212 are configured as high impedance.
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 40 of 74 ? 2015 dialog semiconductor gmbh control interfaces 13.4 all the features of DA9211 and da9212 can be controlled by sw through a serial control interfaces . the communication is selectable to be either a 2 - wire (i2c compliant) or a 4 - wire connection (spi compliant) via control if_type , which will be selected during the initial otp read. if 4 - wire is selected, the gpio3 and gpi4 are automatically configured as interface pin s . data is shifted into or out of DA9211 and da9212 under the control of the host processor , which also provides the serial clock. in a normal application case t he interface is only configured once from otp values, which are loaded during the initial start - up of DA9211 and da9212 . DA9211 and da9212 reacts only on read/write commands where the transmitted register address (using the actual page bits as a msb address range extensions) is within 0x50 to 0x6 7 , 0xd0 to df, 0x140 to 0x14f and (read only) 0x200 to 0x2 7f . ho st access to registers outside these range s will be ignored . this means there will be no acknowledge after receiving the register address in 2 - wire mode, and so stays hi - z in 4 - wire mode. during debug and production modes write access is available to page 4 (0x200 to 0x27f). DA9211 and da9212 will react only on write commands where the transmitted register address is 0x00, 0x80, 0x100 to0x106 . the host processor must read the content of those registers before writing, thereby changing only the bit fields that are not marked as reserved (the content of the read back comes from the compatible pmic, for example da9063). if the stand_alone bit is asserted (otp bit), DA9211 and da9212 will also react t o read commands. 4 - wire communication 13.4.1 in 4 - wire mode the interface us es a chip - select line (ncs/nss), a clock line (sk), data input (si) and data output line (so). the DA9211 and da9212 register map is split into four pages that each contain up to 128 registers . the register at address zero on each page is used as a page control register. the default active page after turn - on includes registers 0x50 to 0x6f. writing to the page control register changes the active page for all subsequent read/write operations unless an automatic return to page 0 was selected by asserting bit revert . unless the revert bit was asserted after modifying the active page , it is recommended to read back the page control register to ensure that future data exchange is accessing the intended registers. all registers out side the DA9211 and da9212 range are write only, that is, the DA9211 and da9212 will not answer to a read command and the data bus is tri - state (they are implicitly directed to da9063). in particular the information contained in registers 0x105 and 0x106 is used by DA9211 and da9212 to configure the control interface. they must be the same as the main pmic (da9063), so that a write to those registers configures both the main pmic and DA9211 and da9212 at the same time. the default otp settings also need to be identical for a correct operation of the system. the 4 - wire interface features a half - duplex operation , that is , data can be transmitted and received within a single 16 - bit frame at enhanced clock speed (up to 14 mhz). it operates at the clock frequencies provided by the host .
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 41 of 74 ? 2015 dialog semiconductor gmbh figure 37 : schematic of 4 - wire and 2 - wire power manager bus a transmission begins when initiated by the host. reading and writing is accomplished by the use of an 8 - bit command, which is sent by the host prior to the exchanged 8 - bit data. the byte from the host begins shifting in on the si pin under the control of the serial clock sk provided from the host. the first seven bits specify the register address (0x01 to 0x07) that will be written or read b y the host. the register address is automatically decoded after receiving the seventh address bit. the command word ends with an r/w bit, which together with the control bit r/w_pol specifies the direction of the following data exchange. during register writing the host continues sending out data during the following eight sk clocks. for reading , the host stops transmitting and the 8 - bit register is cloc ked out of DA9211 and da9212 during the consecutive eight sk clocks of the frame. address and data are transmitted with msb first. the polarity (active state) of ncs is defined by control bit ncs_pol . ncs resets the interface when inactive and it has to be released between successive cycles. the so output from DA9211 and da9212 is normally in high - impedance state and active only during the second half of read cycles. a pull - up or pull - down resistor may be needed at the so line if a floating logic signal can cause unintended current consumption inside other circuits. table 13 : 4 - wire clock configurations configurations cpha clock polarity cpol clock phase output data is updated at sk edge input data is registered at sk edge 0 (idle low) 0 f alling r ising 0 (idle low) 1 r ising f alling 1 (idle high) 0 r ising f alling 1 (idle high) 1 f alling r ising DA9211 and da9212 s 4 - wire interface offers two further configuration bits. clock polarity ( cpol ) and clock phase ( cpha ) define when the interface will latch the serial data bits. cpol determines whether sk idles high ( cpol = 1) or low ( cpol = 0). cpha determines on which sk edge data is shifted in and out. with cpol = 0 and cpha = 0 , DA9211 and da9212 latch data on the sk rising edge. if the cpha is set to 1 the data is latched on the sk falling edge. cpol and cpha states allow four different combinations of clock polarity and phase . e ach setting is incompatible with the other three. the host and DA9211 an d da9212 must be set to the same cpol and cpha states to communicate with each other. p m i c ( s l a v e ) h o s t p r o c e s s o r s k s o s i n c s / n s s n c s / n s s s i s k s o n c s / n s s v d d i o v d d i o v d d i o s l a v e d e v i c e s i s k s o n c s / n s s v d d i o 4 - w i r e i n t e r f a c e h o s t p r o c e s s o r p m i c p e r i p h e r a l d e v i c e s i s k p e r i p h e r a l d e v i c e s d a s c l s c l s d a v d d i o v d d i o 2 - w i r e i n t e r f a c e
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 42 of 74 ? 2015 dialog semiconductor gmbh figure 38 : 4 - wire host write and read timing ( ncs_pol = 0, cpol = 0, cpha = 0) figure 39 : 4 - wire host write and read timing ( ncs_pol = 0, cpol = 0, cpha = 1) a 0 a 6 a 5 a 4 a 3 a 2 a 1 r / w n d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 n c s s k s i s o 4 - w i r e w r i t e a 0 a 6 a 5 a 4 a 3 a 2 a 1 r / w n n c s s k s i s o 4 - w i r e r e a d d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 l a t c h d a t a h i - z a 0 a 6 a 5 a 4 a 3 a 2 a 1 r / w n d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 n c s s k s i s o 4 - w i r e w r i t e a 0 a 6 a 5 a 4 a 3 a 2 a 1 r / w n n c s s k s i s o 4 - w i r e r e a d d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 l a t c h d a t a h i - z
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 43 of 74 ? 2015 dialog semiconductor gmbh figure 40 : 4 - wire host write and read timing ( ncs_pol = 0, cpol = 1, cpha = 0) figure 41 : 4 - wire host write and read ttiming ( ncs_pol = 0, cpol = 1, cpha = 1) a 0 a 6 a 5 a 4 a 3 a 2 a 1 r / w n d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 n c s s k s i s o 4 - w i r e w r i t e a 0 a 6 a 5 a 4 a 3 a 2 a 1 r / w n n c s s k s i s o 4 - w i r e r e a d d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 l a t c h d a t a h i - z a 0 a 6 a 5 a 4 a 3 a 2 a 1 r / w n d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 n c s s k s i s o 4 - w i r e w r i t e a 0 a 6 a 5 a 4 a 3 a 2 a 1 r / w n n c s s k s i s o 4 - w i r e r e a d d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 l a t c h d a t a h i - z
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 44 of 74 ? 2015 dialog semiconductor gmbh table 14 : 4 - wire interface summary param eters signal lines ncs chip select si serial input data master out slave in so serial output data master in slave out sk transmission clock interface push - pull with tristate supply voltage selected from vddio 1.6 v to 3.3 v data rate effective read/write data up to 7 mbps transmission half - duplex msb first 16 bit cycles 7 - bit address, 1 bit read/write, 8 - bit data configuration cpol c lock polarity cpha c lock phase ncs_pol ncs is active low/high note that r eading the same register at high clock rates directly after writing it does not guarantee a correct value. it is recommended to keep a delay of one frame un til re - accessing a register that has just been written ( for example, by writing/reading another register address in between). 2 - wire communication 13.4.2 t he if_type bit in the interface2 register can be used to configure the DA9211 and da9212 control interface as a 2 - wire serial data interface . in th is case the gpio3 and gpi4 are free for regular input/output functions. DA9211 and da9212 has a configurable device write address (default: 0xd0) and a configurable device read address ( default: 0xd1). s ee control if_base_addr 1 f or details of configurable addresses . t he addr_sel_conf bit is used to configure t he device address as if_base_addr 1 or if_base_addr 2 depending on the voltage level applied at a configurable gpi port (see gpio extender ). the sk port functions as the 2 - wire clock and the si port carries all the power manager bi - directional 2 - wire data. the 2 - wire interface is open - drain supporting multiple devices on a singl e line. the bus lines have to be pulled high by external pull - up resistors ( in the 2 k ? to 20 k ? range). the attached devices only drive the bus lines low by connecting them to ground. as a result two devices cannot conflict if they drive the bus simultane ously. in standard/fast mode the highest frequency of the bus is 400 khz. the exact frequency can be determined by the application and does not have any relation to the DA9211 and da9212 internal clock signals. DA9211 and da9212 will follow the host clock speed within the described limitations , and does not initiate any clock arbitration or slow down. a n automatic interface reset can be triggered using control 2wire_to if the clock signal stops to toggle for more than 35 ms. the interface supports operation compatible to standard, fast, fast - plus and high speed mode of the i2c - bus specification rev 4 . operation in high speed mode at 3.4 mhz requires mode changing in order to s et spike suppression and slope control characteristics to be compatible with the i2c - bus specification. the high speed mode can be enabled on a transfer by transfer basis by sending the master code (0000 1xxx) at the begin of the transfer. DA9211 and da9212 do not make use of clock stretching , and deliver read data without additional delay up to 3.4 mhz. alternatively , pm_if_hsm configures the interface to use high speed mode continuously . in this case, the master code is not required at the begin ning of every transfer. this reduc es the communication overhead on the bus but limits the slaves attachable to the bus to compatible devices.
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 45 of 74 ? 2015 dialog semiconductor gmbh the c ommunication on the 2 - wire bus always takes place between two devices, one acting as the master and the other as the slave. the DA9211 and da9212 will only operate as a slave. in contrast to the 4 - wire mode , the 2 - wire interface has direct access to two pages of the register map (up to 256 addresses). the register at address zero on each page is used as a page control re gister (with the 2 - wire bus ignoring the lsb of control reg_page ). writing to the page control register changes the active page for all subsequent read/write operations unless an automatic return to page 0 was selected by asserting control revert . unless revert was asserted after modifying the active page , it is recommended to read back the page control register to ensure that f uture data exchange is accessing the intended registers. in 2 - wire operation DA9211 and da9212 offer an alternative way to access register page 2 and page 3. it removes the need for preceeding page selection writes by incrementin g the device write/read address by one (default 0xd2/0xd3) for any direct access of page 2 and page 3 (page 0 and 1 access requires the basic write/read device address with the msb of reg_page to be 0). details of the 2 - wire control bus protocol 13.4.3 all data is transmitted across the 2 - wire bus in groups of eight bits. to send a bit the sda line is driven towards the intended state w hile the s cl is low (a low on s da indicates a zero bit). once the s da has settled , the s cl line is brought high and then low. this pulse on s cl clocks the s da bit into the receiver s shift register. a two - byte serial protocol is used containing one byte fo r address and one byte data. data and address transfer are transmitted msb first for both read and write operations. all transmission s begin with the start condition from the master while the bus is in idle state (the bus is free). it is initiated by a high to low transition on the sda line while the scl is in the high state (a stop condition is indicated by a low to high transition on the sda line while the s cl is in the high state). figure 42 : timing of 2 - wire start and stop condition the 2 - wire bus is monitored by DA9211 and da9212 for a valid slave address whenever the interface is enabled. it responds i mmediately when it receives its own slave address. the acknowledge is done by pulling the sda line low during the following clock cycle (white blocks marked with a in figure 43 to figure 47 ). the protocol for a register write from master to slave consists of a s tart condition, a slave address with read/write bit and the 8 - bit register address followed by eight bits of data terminated by a stop condition . DA9211 and da9212 respond to all bytes with acknowledge . this is illustrated in figure 43 . s c l s d a
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 46 of 74 ? 2015 dialog semiconductor gmbh figure 43 : 2 - wire byte write ( sda line) when the host reads data from a register it first has to write to DA9211 and da9212 with the target register address and then read from DA9211 and da9212 with a repeated start or alternatively a second start condition. after receiving the data , the host sends no acknowledge and terminates the transmission with a stop condition . this is illustrated in figure 44 . figure 44 : examples of 2 - wire byte read ( sda line) consecutive (page) read out mode is initiated from the master by sending an acknowledge instead of not acknowledge after receipt of the data word. the 2 - wire control block then increments the address pointer to the next 2 - wire address and sends the data to the master. this enables an unlimited read of data bytes until the master sends a not acknowledge directly after the receipt of data, follo wed by a subsequent stop condition. if a non - existent 2 - wire address is read out , the DA9211 and da9212 will return code zero . this is illustrated in figure 45 . figure 45 : examples of 2 - wire page read ( sda line) note that t he slave address after the repeated start condition must be the same as the previous slave address. consecutive (page) write mode is supported if the master sends several data bytes following a slave register address. the 2 - wire control block then increments the address pointer to the next 2 - wire address, stores the received data and sends an acknowledge until the master sends the stop condition. this is illustrated in figure 46 . slaveadr w regadr a data a p s = start condition a = acknowledge ( low) p = stop condition w = write (low) master to slave slave to master 7 - bits 1 - bit 8 - bits 8 - bits a s s slaveadr w a regadr a slaveadr a s = start condition a = acknowledge ( low) sr = repeated start condition a * = no a cknowledge p = stop condition w = write (low) r = read (high) master to slave 7 - bits 1 - bit 8 - bits 7 - bits data a * sr r 1 - bit 8 - bits slaveadr a 7 - bits data p s r 1 - bit 8 - bits p a * slave to master s slaveadr w a regadr p 7 - bits 1 - bit 8 - bits a s slaveadr w a regadr a slaveadr a s = start condition a = acknowledge (low) sr = repeat start condition a * = no acknowledge p = stop condition w = write (low) r = read (high) master to slave slave to master 7 - bits 1 bit 8 - bits 7 - bits data a sr r 1 - bit 8 - bits s slav eadr w a regadr a slaveadr a 7 - bits 1 - bit 8 - bits 7 - bits data p s r 1 - bit 8 - bits p a a * p data data a a * data 8 - bits 8 - bits 8 - bits
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 47 of 74 ? 2015 dialog semiconductor gmbh figure 46 : 2 - wire page write ( sda line) via control write_mode an alternate write mode can be configured. r egister address es and data are sent in alternation like in figure 47 to support host repeated write operations that access several non consecutive registers. data will be stored at the previously received register address . an update of write_mode can not be done without interruption within a transmission frame. thus, if not previously selected or not set as otp default, the activation of repeated write must be done with a regular write on write_mode followed by a stop condition. the next frame after a start condition can be written in repeated write. figure 47 : 2 - wire repeated write (sda line) if a new start or stop condition occurs within a message, the bus will return to idle - mode. s sla veadr w a regadr a data a s = start condition a = acknowledge (low) sr = repeat start condition a * = no acknowledge p = stop condition w = write (low) r = read (high) master to slave slave to master 7 - bits 1 bit 8 - bits 8 - bits data a 1 - bit 8 - bits a p data . a 8 - bits repeated writes s sla veadr w a regadr a data a s = start condition a = acknowledge (low) sr = repeat start condition a * = no acknowledge p = stop condition w = write (low) r = read (high) master to slave slave to master 7 - bits 1 bit 8 - bits 8 - bits regadr a 1 - bit 8 - bits a p data . a 8 - bits repeated writes
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 48 of 74 ? 2015 dialog semiconductor gmbh internal temperature supervision 13.5 to protect DA9211 and da9212 from damage due to excessive power dissipation , the internal temperature is continuously monitored. there are three temperature thresholds, table 15 : over - temperature thresholds temperature threshold typical temperature setting interrupt event status bit masking bit temp_warn 125 c e_temp_warn temp_warn m_temp_warn temp_crit 140 c e_temp_crit temp_crit m_temp_crit temp_por 150 c when the junction temperature reaches the temp_warn threshold, DA9211 and da9212 will assert the bit temp_warn and will generate the event e_temp_warn. if not masked using bit m_temp_warn, the output port nirq will be asserted. the status bit temp_warn will remain asserted as long as the junction temperature remains higher than temp_ warn. when the junction temperature increases further to temp_crit , DA9211 and da9212 will immediately disable the buck converter, assert the bit temp_crit , and will generate the event e_temp_crit. if not masked via bit m_temp_cr it, the output port nirq will be asserted. the status bit temp_crit will remain asserted as long as the junction temperature remains higher than temp_crit. the buck converter will be kept disabled as long as the junction temperature is above temp_crit . it will not be automatically re - enabled even after the temperature drops below the valid threshold (even if the controlling gpi is asserted). a direct write into bucka_en or buckb_en , or a toggling of the controlling gpi , is needed to enable the buck conve rter . whenever the junction temperature exceeds temp_por, a power on reset to the digital core is immediately asserted, which will stops all functionalities of DA9211 a nd da9212 . this is needed to prevent possible permanent damag e in the case of a rapid temperature increase.
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 49 of 74 ? 2015 dialog semiconductor gmbh 14. register d efinitions register m ap 14.1 table 16 : register m ap all bits loaded from otp are marked in bold a ddr f unc t io n 7 6 5 4 3 2 1 0 0x00 p a ge_con revert write_m ode reserved reserved 0x50 sta tus_a reserved reserved reserved gp i4 gp i3 gp i2 gp i1 gp i0 0x51 sta tus_b reserved reserved ov_curr_b ov_curr_a tem p _crit tem p _wa rn p wrgood_b p wrgood_a 0x52 event_a reserved e_uvlo_io reserved e_gp i4 e_gp i3 e_gp i2 e_gp i1 e_gp i0 0x53 event_b reserved reserved e_ov_curr_b e_ov_curr_a e_tem p _crit e_tem p _wa rn e_p wrgoodb e_p wrgood_a 0x54 m a sk_a reserved m _ uv lo _ io reserved m _ g p i4 m _ g p i3 m _ g p i2 m _ g p i1 m _ g p i0 0x55 m a sk_b reserved reserved m _ o v _ c ur r _ b m _ o v _ c ur r _ a m _ t e m p _ c r it m _ t e m p _ wa r n m _ p wr g o o d _ b m _ p wr g o o d _ a 0x56 control_a v _ lo c k 0x57 reserved reserved reserved reserved reserved reserved reserved reserved reserved 0x58 gp io0-1 g p i1_ m o d e g p i1_ t y p e g p i0 _ m o d e g p i0 _ t y p e 0x59 gp io2-3 g p io 3 _ m o d e g p io 3 _ t y p e g p io 2 _ m o d e g p io 2 _ t y p e 0x5a gp io4 reserved reserved g p i4 _ m o d e g p i4 _ t y p e 0x5b reserved reserved reserved reserved reserved 0x5c reserved reserved reserved reserved reserved reserved reserved reserved reserved 0x5d b ucka _cont reserved v b uc ka _ s e l b uc ka _ p d _ d is b uc ka _ e n 0x5e b uckb _cont reserved v b uc kb _ s e l b uc kb _ p d _ d is b uc kb _ e n 0x80 p a ge_con revert write_m ode reserved reserved reserved 0xd0 b uck_ilim 0xd1 b ucka _conf 0xd2 b uckb _conf 0xd3 b uck_conf reserved reserved reserved p h _ s h _ e n _ b p h _ s h _ e n _ a p h a s e _ s e l_ b 0xd4 reserved reserved reserved reserved reserved reserved reserved reserved reserved 0xd5 vb ucka _m a x reserved 0xd6 vb uckb _m a x reserved 0xd7 vb ucka _a reserved 0xd8 vb uckb _b reserved 0xd9 vb uckb _a reserved 0xda vb uckb _b reserved 0x100 p a ge_con revert write_m ode reserved reserved reserved 0x101 otp _cont reserved reserved reserved reserved p c_done otp _a p p s_rd reserved otp _tim 0x102 reserved reserved reserved reserved reserved reserved reserved reserved reserved 0x103 reserved reserved reserved reserved reserved reserved reserved reserved reserved 0x104 reserved reserved reserved reserved reserved reserved reserved reserved reserved 0x105 interfa ce r / w_ p o l c p h a c p o l nc s _ p o l 0x106 interfa ce2 if _ t y p e p m _ if _ h s m p m _ if _ f m p p m _ if _ v reserved reserved reserved reserved 0x140 otp _cont2 o t p _ c o n f _ lo c k o t p _ a p p s _ lo c k reserved reserved reserved reserved reserved reserved 0x141 otp _a ddr 0x142 otp _da ta 0x143 config_a reserved reserved reserved 2 wir e _ t o g p i_ v reserved ir q _ t y p e ir q _ le v e l 0x144 config_b uv lo _ io _ d is p g b _ d v c _ m a s k p g a _ d v c _ m a s k reserved 0x145 config_c reserved reserved reserved g p i4 _ p up d g p io 3 _ p up d g p io 2 _ p up d g p i1_ p up d g p i0 _ p up d 0x146 config_d 0x147 config_e s t a n d _ a lo n e s la v e _ s e l reserved reserved reserved 0x148 config_f reserved reserved if _ b a s e _ a d d r 2 o c a _ m a s k register page 2 reg_p a ge if _ b a s e _ a d d r 1 o s c _ t un e otp _a ddr otp _da ta r e a d y b _ c o n f b uc ka _ p g _ s e l b uc kb _ p g _ s e l r e a d y a _ c o n f o c b _ m a s k s le w_ r a t e _ b b uc kb _ ilim b uc kb _ d o wn _ c t r l b uc kb _ up _ c t r l v b uc kb _ a v b uc kb _ b b uc kb _ m o d e b uc ka _ d o wn _ c t r l b uc ka _ up _ c t r l b uc ka _ m o d e v b uc kb _ m a x p h a s e _ s e l_ a v b uc ka _ a v b uc ka _ b reg_p a ge b uc ka _ ilim g p io 2 _ p in reserved g p i4 _ p in reserved reserved v b uc ka _ m a x v b uc ka _ g p i v b uc kb _ g p i b uc kb _ g p i register page 1 a d d r _ s e l_ c o n f b uc ka _ g p i register page 0 reg_p a ge s le w_ r a t e _ a d e b o un c in g g p i1_ p in g p i0 _ p in g p io 3 _ p in
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 50 of 74 ? 2015 dialog semiconductor gmbh register definitions 14.2 register page control 14.2.1 register bit type label def description 0x00 page_con 7 r/w revert 0 resets reg_page to 000 after read/write access has finished 6 r/w write_mode 0 2 - wire multiple write mode ( note 1 ) 0: page write mode 1: repeated write mode 5:3 r/w (reserved) 000 3:0 r/w reg_page 000 000: selects register 0x01 to 0x3f 001: selects register 0x81 to 0xcf 010: selects register 0x101 to 0x1cf >010: reserved for production and test note 1 not used for 4 - wire - if register page 0 14.2.2 14.2.2.1 system control and event the status registers report the current value of the various signals at the time that it is read out. register bit type label def description 0x 50 status_a 7 :5 r (reserved) 0 00 4 r gpi4 0 gpi4 level 3 r gpi 3 0 gpi3 level 2 r gpi 2 0 gpi2 level 1 r gpi 1 0 gpi1 level 0 r gpi 0 0 gpi 0 level register bit type label def description 0x 51 status_b 7 :6 r (reserved) 0 0 5 r ov_curr_b 0 asserted as long as the current limit for b uck b is hit 4 r ov_curr_a 0 asserted as long as the current limit for buck a is hit 3 r temp_crit 0 asserted as long as the thermal shutdown threshold is reached 2 r temp_warn 0 asserted as long as the thermal warning threshold is reached 1 r pwrgood_b 0 asserted as long a s the buck b output voltage is in range
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 51 of 74 ? 2015 dialog semiconductor gmbh register bit type label def description 0 r pwrgood_a 0 asserted as long a s the buck a output voltage is in range the event registers hold information about events that have occurred in DA9211 and da9212 . events are triggered by a change in the status register which contains the status of monitored signals. w hen an event bit is set in the ev ent register , the irq signal is asserted unless the event is masked by a bit in the mask register. the irq triggering event register will be cleared from the host by writing back its read value. new events occurring during clearing will be delayed before they are passed to the event register, ensuring that the host controller does not miss them. register bit type label def description 0x 52 event_a 7 r (reserved) 0 6 r e_uvlo_io 0 uvlo_io caused the event 5 r (reserved) 0 4 r e_gpi4 0 gpi 4 event according to active state setting 3 r e_ gpi 3 0 gpi 3 event according to active state setting 2 r e_ gpi 2 0 gpi 2 event according to active state setting 1 r e_ gpi 1 0 gpi 1 event according to active state setting 0 r e_ gpi 0 0 gpi0 event according to active state setting register bit type label def description 0x 53 event_b 7 :6 r (reserved) 0 0 5 r e_ov_curr_b 0 ov_curr buck b caused event 4 r e_ov_curr_a 0 ov_curr buck a caused event 3 r e_temp_crit 0 temp_crit caused event 2 r e_temp_warn 0 temp_warn caused event 1 r e_pwrgood_b 0 pwrgood loss at buck b caused event 0 r e_pwrgood_a 0 pwrgood loss at buck a caused event
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 52 of 74 ? 2015 dialog semiconductor gmbh register bit type label def description 0x 54 mask_a 7 r/w (reserved) 0 6 r/w m_uvlo_io 0 mask uvlo_io caused nirq 5 r/w (reserved) 0 4 r/w m_gpi4 0 mask s nirq interrupt at gpi 4 3 r/w m_gpi3 0 mask s nirq interrupt at gpi 3 2 r/w m_gpi2 0 masks nirq interrupt at gpi 2 1 r/w m_gpi1 0 masks nirq interrupt at gpi 1 0 r/w m_gpi0 0 masks nirq interrupt at gpi0 register bit type label def description 0x 55 mask_b 7 :6 r/w (reserved) 0 0 5 r/w m_ov_curr_b 0 ov_curr b uck b caused event 4 r/w m_ov_curr_a 0 ov_curr b uck a caused event 3 r/w m_temp_crit 0 temp_crit caused event 2 r/w m_temp_warn 0 temp_warn caused event 1 r/w m_pwrgood_b 0 pwrgood b uck b caused event 0 r/w m_pwrgood_a 0 pwrgood b uck a caused event
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 53 of 7 4 ? 2015 dialog semiconductor gmbh register bit type label def description 0x 56 control_a 7 r/w v_lock 0 0: allows host writes into registers 0xd0 to 0x14f 1: disables register 0xd0 to 0x14f re - programming from control interfaces 6:5 r/w slew_rate_b 1 0 buck b dvc slewing is executed at 00: 10mv every 4.0 s 01: 10mv every 2.0 s 10: 10mv every 1.0 s 11: 10mv every 0.5 s 4:3 r/w slew_rate_a 1 0 buck a dvc slewing is executed at 00: 10mv every 4.0 s 01: 10mv every 2.0 s 10: 10mv every 1.0 s 11: 10mv every 0.5 s 0:2 r/w debounce 0 11 input signals debounce time: 000: no debounce time 001: 0.1 ms 010: 1.0 ms 011: 10 ms 100: 50 ms 101: 250 ms 110: 500 ms 111: 1000 ms 14.2.2.2 gpio control register bit type label def description 0x 58 gpi0 - 1 7 r/w gpi1_mode 0 0: gpi: debouncing off 1: gpi: debouncing on 6 r/w gpi1_type 1 0: gpi: active low 1: gpi: active high 5:4 r/w gpi1_pin 00 pin assigned to: 00: gpi >00: reserved 3 r/w gpi0_mode 0 0: gpi: debouncing off 1: gpi: debouncing on 2 r/w gpi0_type 1 0: gpi: active low 1: gpi: active high 1:0 r/w gpi0_pin 00 pin assigned to: 00: gpi 01: t rack enable 1x : reserved
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 54 of 74 ? 2015 dialog semiconductor gmbh register bit type label def description 0x 59 gpio2 - 3 7 r/w gpio3_mode 0 0: gpi: debouncing off gpo: sets output to passive level 1: gpi: debouncing on gpo: sets output to active level 6 r/w gpio3_type 1 0: gpi /gpo : active low 1: gpi /gpo : active high 5:4 r/w gpio3_pin 00 pin assigned to: 00: gpi 01: reserved 10: gpo (open drain) 11: gpo (push - pull) 3 r/w gpio2_mode 0 0: gpi: debouncing off gpo: sets output to passive level 1: gpi: debouncing on gpo: sets output to active level 2 r/w gpio2_type 1 0: gpi /gpo : active low 1: gpi /gpo : active high 1:0 r/w gpio2_pin 00 pin assigned to: 00: gpi 01: reserved 10: gpo (open drain) 11: gpo (push - pull) register bit type label def description 0x 5a gpi4 7 :4 r/w (reserved) 0 000 3 r/w gpi4_mode 0 0: gpi: debouncing off 1: gpi: debouncing on 2 r/w gpi4_type 1 0: gpi: active low 1: gpi: active high 1:0 r/w gpi4_pin 0 0 pin assigned to: 00: gpi 01: reserved 1x : reserved
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 55 of 74 ? 2015 dialog semiconductor gmbh 14.2.2.3 regulators control register bit type label def description 0x 5d bucka_con t 7 r/w (reserved) 0 6:5 r/w vbucka_gpi 00 selects the gpi that specifies the target voltage of vbucka. this is vbuck a _a on active to passive transition, vbucka_b on passive to active transition. active high/low is controlled by gpix_type. 00: not controlled by gpio 01: gpio 1 controlled 10: gpi o 2 controlled 11: gpio4 controlled 4 r/w vbucka_sel 0 buck a voltage is selected from (ramping): 0: vbucka_a 1: vbuck a _b 3 r/w bucka_pd_dis 0 0: enable pull - down resistor of buck a when the buck is disabled 1: disable pull - down resistor of buck a when the buck is disabled 2:1 r/w bucka_gpi 00 gpio enables the buck a on passive to active state transition, disables the buck a on active to passive state transition 00: not controlled by gpio 01: gpio0 controlled 10: gpio 1 controlled 11: gpio 3 contro lled 0 r/w bucka_en 0 0: buck a disabled 1: buck a enabled register bit type label def description 0x 5e buckb_con t 7 r/w (reserved) 0 6:5 r/w vbuckb_gpi 00 selects the gpi that specifies the target voltage of vbuckb. this is vbuck b _a on active to passive transition, vbuckb_b on passive to active transition. active high/low is controlled by gpix_type. 00: not controlled by gpio 01: gpio 1 controlled 10: gpio 2 controlled 11: gpio4 controlled 4 r/w vbuckb_sel 0 buck a voltage is selected from (ramping): 0: vbuckb_a 1: vbuck b _b
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 56 of 74 ? 2015 dialog semiconductor gmbh register bit type label def description 3 r/w buckb_pd_dis 0 0: enable pull - down resistor of buck b when the buck is disabled 1: disable pull - down resistor of buck b when the buck is disabled 2:1 r/w buckb_gpi 00 gpio enables the buck b on passive to active state transition, disables the buck b on active to passive state transition 00: not controlled by gpio 01: gpio0 controlled 10: gpio 1 controlled 11: gpio 3 controlled 0 r/w buckb_en 0 0: buck b disabled 1: buck b enabled
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 57 of 74 ? 2015 dialog semiconductor gmbh register page 1 14.2.3 register bit type label def description 0x 80 page_con 7 r/w revert 0 resets reg_page to 000 after read/write access has finished 6 r/w write_mode 0 2 - wire multiple write mode 0: page write mode 1: repeated write mode 5:3 r/w (reserved) 000 3:0 r/w reg_page 000 000: selects register 0x01 to 0x3f 001: selects register 0x81 to 0xcf 010: selects register 0x101 to 0x1cf >010: reserved for production and test 14.2.3.1 regulators settings register bit type label def description 0x d0 buck_ilim 7 :4 r/w buckb_ilim 10 0 1 current limit per phase: 0000: 20 00 ma 0001: 22 00 ma 0010: 24 00 ma continuing through 1001: 3800 ma to 1110: 4 8 00 ma 1111: 50 00 ma 3:0 r/w bucka_ilim 10 0 1 current limit per phase: 0000: 20 00 ma 0001: 22 00 ma 0010: 24 00 ma continuing through 1001: 3800 ma to 1110: 4 8 00 ma 1111: 50 00 ma
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 58 of 74 ? 2015 dialog semiconductor gmbh register bit type label def description 0x d1 bucka_con f 7:5 r/w bucka_down_ ctrl 111 buck a v oltage ramping during power down 000: 1.25 mv/s 001: 2.5 mv/s 010: 5 mv/s 011: 10 mv/s 100: 20 mv/s 101: 30 mv/s 110: 40 mv/s 111: no ramped power down 4:2 r/w bucka_up_ctr l 100 buck a v oltage ramping during start up 000: 1.25 mv/s 001: 2.5 mv/s 010: 5 mv/s 011: 10 mv/s 100: 20 mv/s ( note 1 ) 101: 30 mv/s 110: 40 mv/s 111: target voltage applied immediately (no soft start) 1:0 r/w bucka_mode 10 00: reserved 01: reserved 10: buck a always operates in pwm mode 11: automatic m ode note 1 settings higher than 20 mv/s may cause significant overshoot
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 59 of 74 ? 2015 dialog semiconductor gmbh register bit type label def description 0x d2 buckb_con f 7:5 r/w buck b _down_ ctrl 111 buck b v oltage ramping during power down 000: 1.25 mv/s 001: 2.5 mv/s 010: 5 mv/s 011: 10 mv/s 100: 20 mv/s 101: 30 mv/s 110: 40 mv/s 111: no ramped power down 4:2 r/w b uckb _up_ctr l 100 buck b v oltage ramping during start up 000: 1.25 mv/s 001: 2.5 mv/s 010: 5 mv/s 011: 10 mv/s 100: 20 mv/s ( note 1 ) 101: 30 mv/s 110: 40 mv/s 111: target voltage applied immediately (no soft start) 1:0 r/w buck b _mode 10 00: reserved 01: reserved 10: buck b always operates in pwm mode 11: automatic m ode note 1 settings higher than 20mv/s may cause significant overshoot
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 60 of 74 ? 2015 dialog semiconductor gmbh register bit type label def description 0x d3 buck_conf 7:5 r/w (reserved) 0 00 4 r/w ph_sh_en_b 1 enable current dependant phase shedding in pwm for buck b 3 r/w ph_sh_en_a 1 enable current dependant phase shedding in pwm for buck a 2 r/w phase_sel_b 1 phase selection for buck b i n pwm 0: 1 phase is selected 1: 2 phases are selected 1 :0 r/w phase_sel_a 11 phase selection for buck a i n pwm mode . settings >01 apply only for DA9211 otherwise the number of phases is limited to max 2 00: 1 phase is selected 01: 2 phases are selected 10: 3 phases are selected (uneven 0/90/180 phase shift) 11: 4 phases are selected register bit type label def description 0x d5 vbucka_ma x 7 r/w (reserved) 0 6:0 r vbucka_max 0x7f sets the maximum voltage allowed for buck a (otp programmed, access only in test mode) 0000000: 0.30 v 0000001: 0.31 v 0000010: 0.32 v continuing through 1000110: 1.0 v to 1111101: 1.55 v 1111110: 1.56 v 1111111: 1.57 v
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 61 of 74 ? 2015 dialog semiconductor gmbh register bit type label def description 0x d6 vbuckb_ma x 7 r/w (reserved) 0 6:0 r vbuck b _max 0x7f sets the maximum voltage allowed for buck b (otp programmed, access only in test mode) 0000000: 0.30 v 0000001: 0.31 v 0000010: 0.32 v continuing through 1000110: 1.0 v to 1111101: 1.55 v 1111110: 1.56 v 1111111: 1.57 v register bit type label def description 0x d7 vbucka_a 7 r/w (reserved) 0 6:0 r /w vbucka_a 0x46 0000000: 0.30 v 0000001: 0.31 v 0000010: 0.32 v continuing through 1000110: 1.0 v to 1111101: 1.55 v 1111110: 1.56 v 1111111: 1.57 v
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 62 of 74 ? 2015 dialog semiconductor gmbh register bit type label def description 0x d8 vbucka_b 7 r/w (reserved) 0 6:0 r /w vbucka_ b 0x46 0000000: 0.30 v 0000001: 0.31 v 0000010: 0.32 v continuing through 1000110: 1.0 v to 1111101: 1.55 v 1111110: 1.56 v 1111111: 1.57 v register bit type label def description 0x d9 vbuckb_a 7 r/w (reserved) 0 6:0 r /w vbuck b _ a 0x46 0000000: 0.30 v 0000001: 0.31 v 0000010: 0.32 v continuing through 1000110: 1.0 v to 1111101: 1.55 v 1111110: 1.56 v 1111111: 1.57 v
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 63 of 74 ? 2015 dialog semiconductor gmbh register bit type label def description 0x da vbuckb_b 7 r/w (reserved) 0 6:0 r /w vbuck b _ b 0x46 0000000: 0.30 v 0000001: 0.31 v 0000010: 0.32 v continuing through 1000110: 1.0 v to 1111101: 1.55 v 1111110: 1.56 v 1111111: 1.57 v
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 64 of 74 ? 2015 dialog semiconductor gmbh register page 2 14.2.4 register bit type label def description 0x 100 page_con 7 r/w revert 0 resets reg_page to 000 after read/write access has finished 6 r/w write_mode 0 2 - wire multiple write mode 0: page write mode 1: repeated write mode 5:3 r/w (reserved) 000 3:0 r/w reg_page 000 000: selects register 0x01 to 0x3f 001: selects register 0x81 to 0xcf 010: selects register 0x101 to 0x1cf >010: reserved for production and test 14.2.4.1 interface and otp settings (shared with da9063) register bit type label def description 0x 101 otp_cont 7:4 r/w (reserved) 0000 3 r/w pc_done 0 asserted from power commander software after the emulated otp read has finished, automatically cleared when leaving emulated otp read 2 r /w otp_apps_rd 0 reads on assertion application specific registers 0x105, 0x106, 0x143 to 0x14 9 and otp_apps_lock) from otp 1 r/w (reserved) 0 0 r/w otp_tim 0 otp read timing: 0: normal read 1: marginal read (for otp fuse verification)
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 65 of 74 ? 2015 dialog semiconductor gmbh register bit type label def description 0x 105 interface 7:4 r /w if_base_addr 1 1101 4 msb of 2 - wire control interfaces base address xxxx0000 1101 0000 = 0xd0 write address of pm 2 - wire interface (page 0 and 1) 1101 0001 = 0xd1 read address of pm 2 - wire interface (page 0 and 1) 1101 0010 = 0xd2 write address of pm - 2 - wire interface (page 2 and 3) 1101 0011 = 0xd3 read address of pm - 2 - wire interface (page 2 and 3) code 0000 is reserved for unprogrammed otp (triggers start - up with hardware default interface address) 3 r /w r/w_pol 1 4 - wire: read/write bit polarity 0: host indicates reading access via r/w bit = 0 1: host indicates reading access via r/w bit = 1 2 r /w cpha 0 4 - wire interface clock phase (see table 13 ) 1 r /w cpol 0 4 - wire interface clock polarity 0 : sk is low during idle 1: sk is high during idle 0 r /w ncs_pol 1 4 - wire chip select polarity 0: ncs is low active 1: ncs is high active
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 66 of 74 ? 2015 dialog semiconductor gmbh register bit type label def description 0x 106 interface2 7 r /w er or! book ma rk not defined. if_type 1 0: power manager interface is 4 - wire . automatically configures gpio3 and gpi4 as interface signals. the gpio configuration is overruled. 1: power manager interface is 2 - wire 6 r/w pm_if_hsm 0 enables continuous high speed mode on 2 - wire interface if asserted (no master code reguired) 5 r/w pm_if_fmp 0 enables 2 - wire interface operating with fast mode+ timings if asserted 4 r/w pm_if_v 0 0: power manager interface in 2 - wire mode is supplied from vddcore (4 - wire always from vddio ) 1: power manager interface in 2 - wire mode is supplied from vddio (4 - wire always from vddio ) 0:3 r/w (reserved) 0000 14.2.4.2 otp fusing registers register bit type label def description 0x 140 otp_cont2 7 r /w otp_conf_loc k 0 0: registers 0x54 to 0x5e and 0xd0 to 0xda are not locked for otp programming ( should be selected for unmarked evaluation samples) 1: registers 0x54 to 0x5 e and 0xd0 to 0xd a are locked in otp (no further fusing possible) 6 r /w otp_apps_loc k 0 0: registers 0x105, 0x106, 0x143 to 0x149 are not locked for otp programming ( should be selected for unmarked evaluation samples) 1: registers 0x105, 0x106, 0x143 to 0x14 9 are locked in otp (no further fusing possible) 5 :0 r/w (reserved) 0 000 00 register bit type label def description 0x 141 otp_addr 7 :0 r /w otp_addr 0x00 otp array address register bit type label def description 0x 142 otp_data 7 :0 r /w otp_data 0x00 otp read/write data otp_data written to otp_addr selects the ic and accepts unlock sequence (1 + 3 bytes)
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 67 of 74 ? 2015 dialog semiconductor gmbh 14.2.4.3 application configuration settings register bit type label def description 0x 143 config_a 7:5 r /w (reserved) 000 4 r/w 2wire_to 1 enables automatic reset of 2 - wire interface if the clock stays low for >35 ms 0: disabled 1: enabled 3 r/w gpi_v 0 gpis are supplied from: 0: vddcore 1: vddio 2 r/w (reserved) 0 1 r/w irq_type 1 nirq output port is: 0: push - pull 1: open drain (requires external pull - up resistor) 0 r/w irq_level 0 nirq output port is: 0: active low 1: active high
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 68 of 74 ? 2015 dialog semiconductor gmbh register bit type label def description 0x 144 config_b 7 r /w uvlo_io_dis 0 disable the uvlo for the vddio rail and its comparator (suggested for rail voltages different to 1.8 v and to save quiescent current) 6 r/w pgb_dvc_mas k 0 power - good configuration for buck b 0: power - good signal not masked during dvc transitions 1: power - good signal masked during dvc transitions (keep previous status) 5 r/w pga_dvc_mas k 0 power - good configuration for buck a 0: power - good signal not masked during dvc transitions 1: power - good signal masked during dvc transitions (keep previous status) 4:3 r/w ocb_mask 00 over current configuration for buck b 00: event generation due to over current hit is always active during dvc transitions of the buck converter 01: event generation due to over current hit is masked during dvc transitions of the buck converter + 2 s extra masking at the end 10: event generation due to over current hit is masked during dvc transitions of the buck converter + 10 s extra masking at the end 11: event generation due to over current hit is masked during dvc transitions of the buck converter + 50 s extra masking at the end 2: 1 r/w oca_mask 00 over current configuration for buck a 00: event generation due to over current hit is always active during dvc transitions of the buck converter 01: event generation due to over cur rent hit is masked during dvc transitions of the buck converter + 2 s extra masking at the end 10: event generation due to over current hit is masked during dvc transitions of the buck converter + 10 s extra masking at the end 11: event generation due to over current hit is masked during dvc transitions of the buck converter + 50 s extra masking at the end 0 r/w (reserved) 0
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 69 of 74 ? 2015 dialog semiconductor gmbh register bit type label def description 0x 145 config_c 7 :5 r/w (reserved) 0 00 4 r/w gpi 4_pupd 0 0: gpi: pull - down resistor disabled 1: gpi: pull - down resistor enabled 3 r/w gpio3_pupd 0 0: gpi: pull - down resistor disabled gpo (open drain): pull up resistor disabled (external pull - up resistor) 1: gpi: pull - down resistor enabled gpo (open drain): pull up resistor 2 r/w gpio2_pupd 0 0: gpi: pull - down resistor disabled gpo (open drain): pull up resistor disabled (external pull - up resistor) 1: gpi: pull - down resistor enabled gpo (open drain): pull up resistor enabled 1 r/w gpi 1_pupd 0 0: gpi: pull - down resistor disabled 1: gpi: pull - down resistor enabled 0 r/w gpi 0_pupd 0 0: gpi: pull - down resistor disabled 1: gpi: pull - down resistor enabled register bit type label def description 0x 146 config_d 7 :6 r/w buckb_pg_sel 0 0 selection of the pg signal for buck b 00: none 01: gpo2 10: gpo3 11: reserved 5: 4 r/w bucka_pg_sel 0 0 selection of the pg signal for buck a 00: none 01: gpo2 10: gpo3 11: reserved 3:2 r/w readyb_conf 0 0 selection of the ready signal for buck b 00: none 01: gpo2 10: gpo3 11: reserved 1: 0 r/w readya_conf 0 0 selection of the ready signal for buck a 00: none 01: gpo2 10: gpo3 11: reserved
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 70 of 74 ? 2015 dialog semiconductor gmbh register bit type label def description 0x 147 config_e 7 r/w stand_alone 0 0: DA9211 and da9212 is used as companion ic to da9063 or da9063 - compliant 1: DA9211 and da9212 is stand alone or as companion ic with another pmu not da9063 - compliant 6 r/w (reserved) 0 5:3 r/w (reserved) 0 00 2: 0 r/w osc_tune 00 0 tune the main 6 mhz oscillator frequency: 000: no tune 001: +180 khz 010: +360 khz 011: +540 khz 100: + 7 20 khz 101: 900 khz 110: 1080 khz 111: 1260 khz register bit type label def description 0x 148 config_f 7:4 r /w if_base_addr 2 1101 if a second i2c address is to be selected on adr_sel_conf, this field configures the second address. 4 msb of 2 - wire control interfaces base address xxxx0000 1101 0000 = 0xd0 write address of pm 2 - wire interface (page 0 and 1) 1101 0 001 = 0xd1 read address of pm 2 - wire interface (page 0 and 1) 1101 0010 = 0xd2 write address of pm - 2 - wire interface (page 2 and 3) 1101 0011 = 0xd3 read address of pm - 2 - wire interface (page 2 and 3) code 0000 is reserved for unprogrammed 1 r /w addr_sel_con f 0 0 selects the gpi for the alternative i2c address selection: 00: none 0 1: gpi0 10: gpi1 11: gpi4
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 71 of 74 ? 2015 dialog semiconductor gmbh 15. application information the following recommended components are examples selected from requirements of a typical application. capacitor selection 15.1 ceramic capacitors are used as bypass capacitors at all vdd and output rails. when selecting a capacitor, especially for types with high capacitance at smallest physical dimension, the dc bias characteristic has to be taken into account. table 17 : recommended capacitor types application value size temp char tol v - rate type vout output bypass 4x 22 f 0402 x5r +/ - 15% +/ - 20% 4 v semco cl05a226mr5nznc 4x 10 f 0402 x5r +/ - 15% +/ - 20% 10 v semco cl05a106mp5nunc vddx bypass 4x 10 f 0603 x5r +/ - 15% +/ - 20% 6.3 v murata grm188r60j106me84 vsys bypass 1x 1 f 0402 x5r +/ - 15% +/ - 10% 10 v murata grm 155r61a105ke15# vddio bypass 1x 100 nf 01005 x5r +/ - 15% 10% 6.3 v semco cl02a104kq2nnn inductor selection 15.2 inductors should be selected based upon the following parameters: rated max. current : usually a coil provides two current limits: the isat specifies the maximum current at which the inductance drops by 30% of the nominal value. the imax is defined by the maximum power dissipation and is applied to the effective current. dc resistance: cri tical for the converter efficiency and should therefore be minim ise d. inductance: given by converter electrical characteristics; 0.47uh for each DA9211 and da9212 phase.
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 72 of 74 ? 2015 dialog semiconductor gmbh table 18 : recommended inductor types applicatio n value size imax(dc) isat tol dc res type buck 4x 0.47 h 2.0x1.6x 1.0 mm 3.6 a 4.1 a +/ - 20% 32 m? toko dfe201610p - h - r47m 4x 0.47 h 2.0x1.6x 1.2 mm 3.8 a 4.2 a +/ - 30% 40 m? toko dfe201612c 1286as - h - r47m 4x 0.47 h 2.5x2.0x 1.0 mm 3.6 a 3.9 a +/ - 20% 35 m? toko dfe252010c 1269as - h - r47m 4x 0.47 h 2.5x2.0x 1.2 mm 4.4 a 4.7 a +/ - 20% 29 m? toko dfe252012c 1239as - h - r47m 4x 0.47 h 2.0x1.6x 1.0 mm 2.7 a 3.5 a +/ - 20% 38 m? tdk tfm201610a r47m 4x 0.47 h 2.5x2.0x 1.0 mm 2.8 a 4.5 a +/ - 20% 34 m? tdk tfm252010a r47m 4x 0.47 h 2.0x1.6x 1.0mm 2.7 a 3.56 a +/ - 20% 38 m? cyntec pife20161t 4x 0.47 h 2.5x2.0x 1.0mm 3.5 a 4.5 a +/ - 20% 34 m? cyntec pife25201t 4x 0.47 h 2.5x2.0x 1.2mm 4.5 a 5.0 a +/ - 20% 23 m? cyntec pife25201b 4x 0.47 h 2.5x2.0x 1.2mm 3.7 a 3.9 a +/ - 20% 25 m? cyntec pst25201b 4x 0.47 h 2.0x2.0x 1.2mm 2.8 a 4.2 a +/ - 30% 30 m? taiyo yuden mdmk2020t r47m 4x 0.47 h 2.5x2.0x 1.2mm 3.9 a 4.8 a +/ - 20% 30 m? taiyo yuden mamk2520t r47m 4x 0.47 h 2.0x1.6x 1.0mm 3.2 a 3.6 a +/ - 20% 32 m? murata lqm2mpnr47mgh 4x 0.47 h 4x4x1.2 mm 8.7 a 6.7 a +/ - 20% 14 m? coilcraft xfl4012 - 471me
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 73 of 74 ? 2015 dialog semiconductor gmbh 16. packa ge i nformation figure 49 : DA9211/12 wl - csp package outline d rawing
DA9211 and da9212 datasheet company confidential data sheet version <3.0> < 07 - jan - 201 5 > cfr0011 - 120 - 00 rev 3 74 of 74 ? 2015 dialog semiconductor gmbh disclaimer information in this document is believed to be accurate and reliable. however, dialog semiconductor does not give any represent ations or warranties, expressed or implied, as to the accuracy or completeness of such information. dialog semiconductor furtherm ore takes no responsibility whatsoever for the content in this document if provided by any information source outside of dialog semiconductor. dialog semiconductor reserves the right to change without notice the information published in this document, including withou t limitation the specification and the design of the related semiconductor products, software and applications. applications, soft ware, and semiconductor products described in this document are for illustrative purposes only. dialog semiconductor makes no representation or warranty that such applications, software and semiconductor products will be suitable for the specified use with out further testing or modification. unless otherwise agreed in writing, such testing or modification is the sole responsibility of the customer and dialog semiconductor excludes all liability in this respect. customer notes that nothing in this document may be construed as a license for customer to use the dialog semi - conductor products, software and applications referred to in this document. such license must be separately sought by customer with dialog semiconductor. all use of dialog semiconductor prod ucts, software and applications referred to in this document are subject to dialog semiconductors standard terms and conditions of sale , unless otherwise stated. ? dialog semiconductor gmbh. all rights rese rved. rohs c ompliance dialog semiconductor complies to directive 2002/95/e c of t he european parliament and of t he council of 27 january 2003 concerning restriction of hazardous substances (rohs). dialog semiconductors statement on rohs can be found on the customer portal https://support.diasemi.com/ . rohs certificates from our sup pliers are available on request. contacting dialog semiconductor germany headquarters dialog semiconductor gmbh phone: +49 7021 805 - 0 united kingdom dialog semiconductor (uk) ltd phone: +44 1793 757700 the netherlands dialog semiconductor b.v. phone: +31 73 640 88 22 north america dialog semiconductor inc. phone: +1 408 727 3200 japan dialog semiconductor k. k. phone: +81 3 5425 4567 taiwan dialog semiconductor taiwan phone: +886 226 580 388 singapore dialog semiconductor singapore phone: +65 64845419 china dialog semiconductor china phone: +852 2607 4271 korea dialog semiconductor korea phone: +82 2 569 2301 email: enquiry@diasemi.com web site: www.dialog - semiconductor.com

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